3D Memory Fin and Gate Oxide Layout for Easier Etching
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Solution Overview
Problem
The challenge in 3D NAND flash memory fabrication is the increasing complexity and cost of planar process techniques as feature sizes approach the lower process limit, limiting memory density, which is addressed by integrating planar transistors and fin field-effect transistors in a 3D structure.
Innovation Solution
The integration of a semiconductor device with a substrate having first and second well regions, where the sum of the thicknesses of the fin and gate oxide layer in the first well region is less than or equal to that of the second well region, allowing for an enlarged etching process window and reduced etching difficulty by forming fins and gate layers with specific thickness relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar process techniques are used to increase memory density, then memory density is improved, but process complexity and cost increase as feature sizes approach the lower process limit
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D FinFET structures by creating vertical fins that extend upward from the substrate. This dimensional change allows memory density to increase vertically rather than requiring further miniaturization of planar features, thereby avoiding the complexity and cost associated with pushing planar process limits.
2Quantity of substance
If feature sizes are reduced to increase memory density in planar NAND flash memory, then memory density is improved, but manufacturing difficulty and cost increase
Solution Approach 1:
Instead of continuing to reduce feature sizes in the planar dimension, the patent creates vertical fins that extend upward from the substrate surface. This allows memory cells to be stacked vertically, increasing density without requiring further reduction of lateral feature sizes, thus avoiding the associated manufacturing difficulties.
3Manufacturing precision
If multiple etching steps with additional masks are used to form fins and gate layers, then manufacturing precision is improved, but process complexity and cost increase
Solution Approach 1:
The patent combines the formation of fins and gate layers into a single etching step by using a unified mask pattern that defines both structures simultaneously. This merging of operations reduces the total number of etching steps and mask applications required, thereby simplifying the process while maintaining the necessary manufacturing precision through the carefully designed mask pattern.
Data Source
AI summary
Examples of the present application provide a semiconductor device, a fabrication method thereof, a 3D memory and a memory device, wherein the semiconductor device includes: a substrate including first fins and second fins; a first gate oxide layer disposed on the first fins; a second gate oxide layer disposed on the second fins, wherein the sum of the thicknesses of the first fin and the first gate oxide layer is less than or equal to the sum of the thicknesses of the second fin and the second gate oxide layer; and a gate layer disposed on the first gate oxide layer and the second gate oxide layer. In the way described above, difficulty of etching process is reduced and yield and performance of products are improved.