Transistor TRIZ Cases
- Semiconductor Fin Contact Structure to Reduce Latch-Up Leakage
Selective liner removal around semiconductor fins cuts charge buildup, easing base contact formation and reducing latch-up leakage.
- Stacked FET Channel Layout for CPP Scaling and Short-Channel Control
Vertically offset source, drain, and gate prongs shrink CPP while using electrostatic doping to sustain drive current and limit short-channel effects.
- Vertical Channel Gate Structure for Dielectric-Metal Isolation
A barrier layer and self-aligned dielectric protrusion isolate the gate dielectric from metal to avoid high-resistance products.
- Multi-Metal CMP Planarization for Matched Semiconductor Contacts
Two-step CMP with tailored acidic slurries and inhibitors levels ruthenium and tungsten or molybdenum contacts within 5 nm.
- Gate-to-Contact Conductive Path Layout for Lower FinFET Resistance
Limiting sidewall dielectric liner height above the upper nanosheet opens a lower-resistance gate-to-contact path and reduces current crowding.
- Nanosheet Transistor Channels With Dielectric Support Layers
Supporting dielectric layers reinforce nanosheet transistor channels during release and contact formation, reducing degradation and contact resistance.
- Battery Subpack Switch Circuit for Fault Decoupling and Addressing
A switch circuit powers subpack microprocessors for address detection, then removes voltage to isolate subpacks when communication faults occur.
- Resonant Turn-Off Control for Low-Overvoltage Switching Elements
By timing turn-off to the commutation circuit resonance, this case cuts parasitic-inductance overvoltage and enables low-loss fast switching.
- IGBT Gate Wiring Layout for Low-Resistance Fast Switching
Stacked multi-metal gate wiring lowers IGBT gate resistance for faster switching while preventing unwanted connections at wiring crossings.
- ALD Gate Spacer Chemistry for Low Capacitance and Etch Resistance
ALD spacer deposition with Si-C-Si bonding lowers effective capacitance while preserving plasma and etch resistivity in metal gate formation.
- Capacitive Substrate Clamp in III-Nitride Transistors for Lower Switching Loss
A capacitive voltage divider clamps substrate potential in III-nitride transistors to cut parasitic switching losses and extend lifetime.
- Power Converter Fault Isolation via Differential Current Peak Sensing
Peak differential current sensing lets the controller isolate DC network faults before capacitor discharge and AC-side current damage converter diodes.
- Backside Contact Structure Using a Wide Placeholder Profile
A wide placeholder shields source/drain regions from wet etchant attack during substrate removal while enabling lower-resistance backside contact formation.
- Adaptive Gate Driver Voltage Control for Faster Semiconductor Switching
Three-stage gate voltage control adapts to current, voltage, and temperature to cut switching loss while maintaining surge voltage safety.
- Cascode SiC JFET Bias Control for Low Loss and SCWT
Dynamic gate biasing in a cascode SiC JFET and Si MOSFET cuts conduction loss in normal use and extends short circuit withstand time.
- High-Side Motor Driver Charge Pump Timing for Lower Switching Loss
Gate-voltage monitoring and timed charge-pump bursts cut continuous switching loss while keeping the high-side transistor on.
- Staggered Dielectric Contact Structure for Self-Aligned FinFET Vias
Selective dual-dielectric growth forms self-aligned contacts and vias that reduce FinFET bridging, misalignment, and contact resistance.
- Ge-Diffused GAA Nanoribbon Channels for PMOS Scaling
Ge diffusion and self-aligned SiGe condensation form GAA nanoribbon PMOS channels with better mobility, short-channel control, and lower cell height.