Capacitive Substrate Clamp in III-Nitride Transistors for Lower Switching Loss
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Solution Overview
Problem
Lateral III-nitride transistors suffer from vertical parasitic capacitor effects leading to unwanted switching losses and high early lifetime failure rates due to defects in epitaxial structures grown on foreign substrates, which are difficult to fabricate with high yield and meet automotive application-level lifetime requirements.
Innovation Solution
Incorporating a capacitive voltage divider circuit with a voltage clamp and/or discharge diode between the source region and substrate to reduce parasitic vertical capacitance, clamping the substrate potential to a positive value and discharging negative potential during transitions, thereby reducing switching losses and improving transistor efficiency and lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-nitride epitaxial structures are grown on foreign substrates such as Si, sapphire, or SiC, then the transistor can be fabricated, but high-quality epitaxial structures are difficult to form resulting in defects that degrade fabrication yield and induce high early lifetime failure rate
Solution Approach 1:
The patent introduces a capacitive voltage divider circuit as an intermediary element between the source region and substrate. This circuit includes a capacitor and resistor network that mediates the voltage distribution, preventing high vertical voltage stress from reaching the epitaxial structure. By adding this intermediary circuit, the system achieves improved reliability without requiring higher epitaxial structure quality.
2Reliability
If high-quality epitaxial structures are achieved, then transistor lifetime is improved, but fabrication yield and manufacturing complexity are negatively impacted due to the difficulty of growing defect-free structures on foreign substrates
Solution Approach 1:
The capacitive voltage divider circuit serves as a protective intermediary that decouples the transistor's operational reliability from the epitaxial structure quality. By introducing this external circuit element, the system can achieve high reliability even with moderate epitaxial quality, thereby improving fabrication yield without sacrificing transistor lifetime.
Solution Approach 2:
The patent changes the voltage distribution parameters by introducing the capacitive voltage divider. This modifies the electrical stress parameters applied to the epitaxial structure, reducing the vertical voltage drop across it. By changing these electrical parameters rather than requiring perfection in material quality, the system achieves high reliability with improved manufacturability.
3Power
If the vertical parasitic capacitor across the epitaxial structure is present, then the transistor structure is complete, but unwanted hard and soft switching losses occur which become more critical at high frequencies
Solution Approach 1:
The capacitive voltage divider circuit acts as an intermediary that redistributes the voltage stress. By placing a capacitor in parallel with the parasitic capacitance and adding series resistors, the circuit mediates the charging and discharging of the parasitic capacitor, reducing the intensity of switching losses.
Solution Approach 2:
The patent changes the time constants and voltage distribution parameters during switching transitions. By carefully selecting the resistor and capacitor values in the voltage divider circuit, the system controls the rate of voltage change across the parasitic capacitor, thereby reducing both hard and soft switching losses while maintaining complete transistor functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive voltage divider circuit reduces vertical voltage drop and parasitic capacitance, enhancing switching efficiency and extending the transistor's lifetime while meeting stringent automotive application requirements.
Implementation Method 1
a capacitive voltage divider circuit electrically connected between the source region and the substrate, wherein in a blocking state of the transistor device, the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value
Implementation Method 2
a discharge diode device electrically connected from the substrate to the source region in a reverse direction, wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on
Data Source
AI summary
A transistor device includes: a substrate; an epitaxial layer stack formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region of the transistor device; a source terminal electrically connected to a source region of the epitaxial layer stack; a drain terminal electrically connected to a drain region of the epitaxial layer stack; a gate terminal electrically connected to a gate structure laterally between the source region and the drain region; a substrate terminal electrically connected to the substrate; and a capacitive voltage divider circuit electrically connected between the source region and the substrate. In a blocking state of the transistor device, the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value. Additional transistor device embodiments are described.