Nanosheet Transistor Channels With Dielectric Support Layers

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Solution Overview

Problem

As semiconductor devices shrink in size, nanostructure transistors face challenges such as mechanical degradation due to external forces during processing, and traditional materials lack sufficient mechanical strength, leading to performance issues like short channel effects and electron tunneling.

Innovation Solution

Incorporating supporting dielectric layers under and/or on nanostructure channels, which enhance mechanical strength, allowing for the use of advanced materials like TMDs and enabling two-dimensional channels, and providing a greater process window for fabrication, reducing mechanical degradation and improving contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If traditional materials are used for nanostructure channels, then manufacturing process is simpler, but mechanical strength is insufficient leading to degradation

Engineering Contradiction:
Improvemechanical strengthVSAvoidstructural complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent combines advanced materials (such as TMDs - transition metal dichalcogenides) with supporting dielectric layers to create a composite nanostructure channel. This composite structure provides both the desired mechanical strength and electrical properties, resolving the contradiction between using simple traditional materials and achieving sufficient mechanical strength.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

Supporting dielectric layers are introduced as intermediary structures between the nanostructure channel and the surrounding environment. These dielectric layers act as mechanical support and protection, enabling the use of advanced fragile materials while maintaining device functionality and reducing mechanical degradation during processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If advanced materials like TMDs are used, then electrical performance is improved, but mechanical degradation increases due to external forces

Engineering Contradiction:
Improveelectrical performanceVSAvoidmechanical degradation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Supporting dielectric layers are incorporated beforehand to cushion and protect the advanced materials (such as TMDs) from external mechanical forces during subsequent processing steps. This prior protection prevents mechanical degradation while allowing the advanced materials to provide their electrical performance benefits.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

Thin dielectric film structures are used to encapsulate and protect the nanostructure channel. These thin films provide mechanical protection against external forces while maintaining the electrical properties of the advanced materials, resolving the contradiction between electrical performance and mechanical durability.

Inventive Principle:
Principle #30Flexible shells and thin films

3Length of moving object

If gate length is reduced for smaller technology nodes, then transistor size decreases, but off current increases due to source/drain electron tunneling

Engineering Contradiction:
Improvegate lengthVSAvoidoff current
Core Design Contradiction:
Length of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent modifies the material parameters and structural parameters of the source/drain regions and channel interface. By changing the material composition and band structure parameters, the tunneling barrier is enhanced, reducing off-current even at reduced gate lengths, thus resolving the contradiction between device scaling and leakage control.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250318200A1Semiconductor device and methods of formation
Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250318200A1 patent drawing
  • US20250318200A1 patent drawing
  • US20250318200A1 patent drawing

AI summary

One or more supporting dielectric layers are included under and/or on a nanostructure channel of a nanostructure transistor. The nanostructure transistor may be formed by forming a nanosheet stack that includes one or more channel layer stacks that are sandwiched between sacrificial layers. The nanostructure channel layer stacks may each include a nanostructure channel layer and one or more dielectric supporting layers under and/or on the nanostructure channel layer. The nanosheet stack is etched to define the nanostructure channels of the nanostructure transistor. An inner spacer process is performed to form inner spacers on sidewalls of the sacrificial layers between the nanostructure channel layer stacks, and source/drain contacts are then formed on sidewalls of the nanostructure channel layer stacks and on the inner spacers. The sacrificial layers are subsequently removed in a nanosheet release process and replaced with a metal gate structure and associated high-k dielectric layers.