Stacked FET Channel Layout for CPP Scaling and Short-Channel Control
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Solution Overview
Problem
The scaling of contacted poly pitch (CPP) in transistor devices is limited by gate length, source/drain contact area, and gate spacer width, hindering further miniaturization.
Innovation Solution
A field-effect transistor (FET) device design featuring vertically offset source, drain, and gate prongs, with overlapping regions for dynamic electrostatic doping, reducing the need for chemical doping and spacer width, and enabling reduced short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET structure with separate source/drain and gate terminals is used, then electrical separation between gate and source/drain is achieved, but CPP scaling is limited by minimum spacer length
Solution Approach 1:
The patent transitions from a planar FET structure to a three-dimensional stacked structure with vertically offset source/drain prongs and gate prongs. This vertical stacking allows the gate and source/drain to be electrically separated in the vertical dimension while maintaining minimal horizontal spacing, enabling CPP scaling below conventional limits.
Solution Approach 2:
The source/drain body is segmented into multiple vertically spaced prongs, and the gate body is segmented into corresponding vertically spaced prongs. This segmentation allows each prong pair to be independently positioned and sized, optimizing electrical separation while minimizing overall footprint and enabling reduced spacer widths.
2Power
If chemical doping concentration is increased to improve drive current, then drive current increases, but sub-threshold-swing degradation worsens
Solution Approach 1:
The patent replaces chemical doping (a chemical process) with electrostatic doping (an electrical field effect). The gate prongs generate electric fields that modulate the carrier concentration in the channel regions between source and drain prongs, enabling drive current control without chemical dopant diffusion that causes sub-threshold-swing degradation.
Solution Approach 2:
The patent changes the doping mechanism from fixed chemical doping to dynamically controllable electrostatic doping. By applying gate voltages to the gate prongs, the carrier concentration in the channel can be precisely controlled, providing high drive current when needed while maintaining good sub-threshold characteristics when the device is off.
3Area of stationary object
If gate length is scaled down to reduce device footprint, then device density increases, but short-channel effects increase
Solution Approach 1:
The patent addresses short-channel effects by moving the gate control from a lateral configuration to a vertical stacked configuration. The gate prongs are positioned vertically above and below the channel regions, providing enhanced electrostatic control over the channel despite reduced horizontal gate length, thereby suppressing short-channel effects while maintaining small device footprint.
Solution Approach 2:
The gate prongs are nested vertically between and around the source/drain prong pairs, with each gate prong positioned to control specific channel regions. This nested arrangement maximizes gate control efficiency within a compact footprint, providing strong electrostatic control that counteracts short-channel effects in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables further CPP scaling by reducing spacer width and chemical doping requirements, improving drive current and reducing sub-threshold-swing degradation while minimizing short-channel effects.
Implementation Method 1
the gate body may be configured to, when the field-effect transistor is switched to an active state, induce, in each channel layer, an electrostatic doping in the first and second common regions and a channel region extending therebetween
Data Source
AI summary
A FET device (100) is provided, the FET device including a substrate (102), a source body (120), a drain body (130) and a set of vertically spaced apart channel layers (150) extending between the source and drain body in a first direction along the substrate (102), the source body (120) comprising a common source body portion (122) arranged at a first lateral side of the set of channel layers (150) and a set of vertically spaced apart source prongs (124) protruding from the common source body portion (122) in a second direction along the substrate (102), transverse to the first direction, the drain body (130) comprising a common source body portion (132) arranged at the first lateral side of the set of channel layers (150) and a set of drain prongs (134) protruding from the common drain body portion (132) in the second direction; and a gate body (140) comprising a common gate body portion (142) arranged at a second lateral side of the channel layer (150), opposite the first lateral side, and a set of gate prongs (144) protruding from the common gate body gate portion (142) in a third direction along the substrate (102), opposite the first direction; wherein each channel layer (150) comprises a first side (150aa, 150ba) and an opposite second side (150ab, 150bb), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs (124a, 134a) and the second side (150ab, 150bb) facing a gate prong (144a, 144b).