IGBT Gate Wiring Layout for Low-Resistance Fast Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing insulated gate bipolar transistors (IGBTs) face challenges in reducing on-resistance and switching loss due to high electrical resistance in gate wiring, which hinders fast switching operations.

Innovation Solution

The IGBT design incorporates a stacked structure for gate wirings with multiple metal layers to reduce electrical resistance, allowing for independent control of three gates and minimizing unwanted electrical connections at intersections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple gate wirings are provided for independent gate control, then switching loss is reduced and switching speed is improved, but electrical resistance of the gate wiring increases causing signal delay

Engineering Contradiction:
Improveswitching speedVSAvoidsignal transmission quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Multiple gate wirings are merged into a single shared wiring path that distributes signals to multiple gate electrodes. This consolidation reduces the total number of separate wirings, lowering overall electrical resistance and preventing signal delay while still enabling independent control of multiple gates through a common signal distribution network.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

A single gate wiring structure is designed to serve multiple functions by distributing control signals to multiple gate electrodes simultaneously. This multi-functional wiring approach reduces the number of dedicated wirings needed, thereby reducing total resistance and improving signal transmission quality while maintaining the capability for independent gate control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple separate gate wirings are used, then independent gate control is achieved, but device complexity and chip area increase

Engineering Contradiction:
Improveindependent gate control capabilityVSAvoidwiring structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple gate wirings into a unified wiring structure that distributes signals to multiple gates. This merging approach reduces device complexity by eliminating redundant wiring paths while preserving the independent gate control capability through intelligent signal distribution within the shared wiring network.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate wiring is designed as a universal structure that can control multiple gates simultaneously. This multi-functional wiring reduces the overall complexity of the device by using a single wiring architecture to perform what would otherwise require multiple separate wiring systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If gate wiring resistance is reduced by using thicker or more conductive materials, then switching speed improves, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveswitching speedVSAvoidmanufacturing simplicity
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

By merging multiple gate wirings into a shared structure, the patent reduces the total amount of conductive material needed and simplifies the manufacturing process. This approach achieves low resistance and fast switching speed without requiring thicker or more expensive materials, as the reduced total wiring length and simplified structure naturally lower resistance while easing manufacturing constraints.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250318166A1Semiconductor device
Publication Date: 2025.10.09 KK TOSHIBA
  • US20250318166A1 patent drawing
  • US20250318166A1 patent drawing
  • US20250318166A1 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a semiconductor layer with a plurality of first and second trenches extending lengthwise in a first direction. A first gate electrode is in each first trench. A second gate electrode is in each second trench. A first gate wiring has an upper metal layer and a lower metal layer and a second gate wiring also has an upper metal layer and a lower metal layer. At position where the first gate wiring and the second gate wiring cross without being electrically connected, the lower metal layer of one the first or second gate wirings and the upper metal layer of the other of the first or second gate wirings are not present.