Gate-to-Contact Conductive Path Layout for Lower FinFET Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and resistance in semiconductor manufacturing processes, particularly in multi-gate devices like FinFETs and GAA transistors, hinder the realization of smaller, faster, and more efficient integrated circuits due to dielectric obstructions in conductive paths from source/drain interconnects to channel regions.
Innovation Solution
A method is employed to form a conductive path with reduced resistance by minimizing dielectric obstructions by limiting the sidewall dielectric liner height to above the uppermost nanosheet channel, using a two-step etch process to etch source/drain features, and ensuring the dielectric sidewall layer does not obstruct current flow, thereby preventing current crowding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric sidewall liner is formed around the source/drain interconnect, then the interconnect is protected and isolated, but the dielectric material obstructs the conductive path and increases resistance
Solution Approach 1:
The patent removes the dielectric sidewall liner material from the region directly adjacent to the channel region, extracting the harmful dielectric obstruction while preserving the protective function in other areas. This creates a localized absence of the dielectric material that allows direct current flow between the interconnect and channel.
Solution Approach 2:
The patent applies different structural qualities to different regions: the dielectric sidewall liner is present in some areas for protection but intentionally absent or reduced in the critical conductive path region. This local modification optimizes both protection and conductivity in their respective zones.
2Reliability
If the sidewall dielectric liner height is increased to provide better coverage, then protection is improved, but current flow into the uppermost nanosheet is obstructed
Solution Approach 1:
The patent modifies the vertical dimension of the dielectric sidewall liner by limiting its height to extend only to a level above the uppermost nanosheet channel rather than covering the entire sidewall. This dimensional adjustment allows current to flow horizontally into the nanosheet without vertical obstruction.
3Ease of manufacture
If conventional etching processes are used to form source/drain features, then manufacturing is simpler, but dielectric obstructions remain in conductive paths
Solution Approach 1:
The patent divides the etching process into multiple sequential steps, where each step removes material selectively to different depths. This segmentation allows precise control over where dielectric material is removed versus where it is retained, creating the desired conductive path without requiring complete process redesign.
Data Source
AI summary
Provided are semiconductor devices with reduced resistance in conductive paths from gates to contacts and methods for fabricating such devices. An exemplary method includes forming an epitaxial feature adjacent to a gate, wherein the gate lies over an uppermost surface of a semiconductor fin at a first vertical height; forming a first dielectric material over the epitaxial feature; forming a capping layer over the first dielectric material; forming a second dielectric material over the capping layer; forming an opening over the epitaxial feature, wherein the opening has a sidewall; and forming a side layer over the sidewall of the opening, wherein the side layer extends to a lowest edge at a second vertical height at or above the first vertical height.