Cascode SiC JFET Bias Control for Low Loss and SCWT
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Solution Overview
Problem
Existing power switching devices face challenges in achieving low on-resistance while maintaining sufficient short circuit withstand time (SCWT), often resulting in increased conduction losses and false alarms during short circuit conditions.
Innovation Solution
A cascode switching circuit is employed, combining a normally-on silicon carbide (SiC) JFET and a normally-off silicon (Si) MOSFET, with a gate driver circuit that applies a positive bias under normal conditions to reduce on-resistance and a negative bias during short circuits to extend SCWT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the on-resistance of a cascoded switch is reduced for a given application, then conduction loss decreases and efficiency improves, but the die size increases and cost increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate-to-source voltage of the normally-on transistor. Under normal operating conditions, a positive bias voltage is applied to reduce on-resistance and minimize conduction losses. This dynamic parameter adjustment allows the device to achieve low conduction loss without permanently increasing die size, as the low-resistance state is achieved through electrical biasing rather than physical enlargement.
2Loss of energy
If the on-resistance of a cascoded switch is reduced, then efficiency improves, but short circuit withstand time decreases
Solution Approach 1:
The patent employs dynamics by implementing a gate driver circuit that dynamically switches the bias voltage applied to the normally-on transistor based on operating conditions. During normal operation, positive bias reduces on-resistance for low conduction loss. Upon detecting a short circuit condition, the gate driver rapidly transitions to applying a negative bias voltage, which increases on-resistance to limit fault current and extend short circuit withstand time. This dynamic adaptation resolves the contradiction between efficiency and protection capability.
Solution Approach 2:
The patent changes the electrical parameters of the normally-on transistor by adjusting its gate-to-source voltage. Under normal conditions, a positive bias voltage (e.g., +2V to +5V) reduces the on-resistance to minimize conduction losses and improve efficiency. When a short circuit is detected, the parameter is changed to a negative bias voltage (e.g., -2V to -5V), which increases the on-resistance to limit fault current and extend the short circuit withstand time, thereby resolving the contradiction between efficiency and protection.
3Loss of energy
If a normally-on transistor is used to achieve low on-resistance, then conduction loss reduces, but false alarms occur during short circuit conditions
Solution Approach 1:
The patent implements feedback through a gate driver circuit that monitors the operating state of the power switching device and adjusts the gate-to-source voltage of the normally-on transistor accordingly. During normal operation, the feedback mechanism maintains positive bias for low conduction loss. Upon detecting a short circuit condition through monitoring circuits, the feedback loop triggers a transition to negative bias, which increases on-resistance to limit fault current and prevent false alarms, thus maintaining reliability while achieving low conduction loss during normal operation.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2
AI summary
A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.