Semiconductor Fin Contact Structure to Reduce Latch-Up Leakage
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Solution Overview
Problem
Non-planar MOS devices face challenges in forming contacts to the base region due to reduced design flexibility and charge accumulation at the interface between the liner and semiconductor fin, leading to latch-up effects and leakage paths.
Innovation Solution
The method involves forming semiconductor fins with different dopant types and removing a portion of the liner in the first region to reduce charge accumulation, followed by epitaxy processes to enhance device performance, including the use of epitaxy structures with matching dopants to improve contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a liner is formed over the semiconductor fin to protect the structure during fabrication, then structural integrity is improved, but charge accumulation occurs at the interface leading to leakage paths and latch-up effects
Solution Approach 1:
The patent removes the liner structure from specific regions where charge accumulation occurs. By extracting the liner material (such as silicon nitride) from the interface region between the semiconductor fin and the isolation structure, the harmful charge accumulation is eliminated while maintaining the protective function of the liner in other critical areas.
Solution Approach 2:
The patent applies different liner configurations to different regions of the device. The liner is present in some areas to provide structural protection during fabrication, but absent in other areas where charge accumulation would cause leakage or latch-up effects. This localized differentiation allows simultaneous achievement of structural integrity and electrical performance.
2Ease of manufacture
If conventional contact formation methods are used in non-planar MOS devices, then fabrication simplicity is maintained, but design flexibility is reduced and contact formation to base region becomes challenging
Solution Approach 1:
The patent divides the device structure into distinct regions with different liner configurations. By segmenting the liner presence/absence across different areas, the design achieves flexibility in contact formation to the base region while maintaining overall fabrication simplicity through standardized processes applied to segmented structures.
Solution Approach 2:
The patent utilizes the three-dimensional nature of non-planar MOS devices by strategically placing or removing liner material in vertical and lateral dimensions. This dimensional approach enables improved contact formation to the base region by accessing it from multiple spatial perspectives rather than being constrained to a single planar interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces charge-induced leakage paths and enhances device performance by minimizing latch-up effects and improving contact formation in non-planar MOS devices.
Implementation Method 1
epitaxy processes to enhance device performance, including the use of epitaxy structures with matching dopants
Data Source
AI summary
A device includes a substrate. A first semiconductor fin and a second semiconductor fin are over the substrate, wherein an upper portion of the second semiconductor fin and a lower portion of the second semiconductor fin are made of different materials. A first epitaxy structure is over the first semiconductor fin. A second epitaxy structure is in contact with the upper portion of the second semiconductor fin, wherein sidewalls of the lower portion of the second semiconductor fin are free of coverage by the second epitaxy structure. A liner is in contact with the sidewalls of the lower portion of the second semiconductor fin. An isolation structure between the first and second semiconductor fin, wherein the isolation structure is in contact with the first semiconductor fin and is separated from the second semiconductor fin through the liner.