3D Memory Stack Layout for Density and Fast Access
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Solution Overview
Problem
The demand for increased memory capacity is hindered by the limitations of planar memory cells, which become challenging and costly to scale down, while 3D memory architecture offers a solution to enhance density but faces challenges in integrating high-density storage with fast read and write speeds.
Innovation Solution
A method for forming a 3D memory device by creating a semiconductor structure with interleaved dielectric and sacrificial layers, forming through stack structures for NAND and ferroelectric memory cells, and bonding peripheral circuits to achieve high storage capacity and fast operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertical stacking architecture. Multiple memory layers are stacked vertically with through-stack structures penetrating through all layers, enabling memory density increase without proportionally increasing manufacturing complexity by utilizing the vertical dimension instead of continuing lateral scaling
2Quantity of substance
If 3D memory architecture is used to increase density, then storage capacity improves, but operating speed decreases
Solution Approach 1:
The patent segments the 3D memory structure into distinct functional regions: volatile memory regions (NAND flash) for fast read/write operations and non-volatile memory regions (ferroelectric) for data retention. Through-stack structures provide direct vertical pathways that enable fast access to stored data, combining the high-speed characteristics of volatile memory with the high-density benefits of 3D architecture
Solution Approach 2:
Different regions of the 3D memory stack are assigned different material compositions and functional properties. Some layers use ferroelectric materials for non-volatile storage while other regions use conventional NAND structures for volatile fast storage. This local differentiation allows the system to achieve both high density and fast operating speeds by accessing the appropriate memory type based on operational requirements
3Adaptability or versatility
If multiple types of memory cells are integrated in 3D structure, then functionality and performance improve, but manufacturing process complexity increases
Solution Approach 1:
The patent forms through-stack structures that penetrate through the entire 3D memory stack before the final memory cell formation. These pre-formed structures serve as common pathways for multiple memory types, establishing the vertical interconnect architecture early in the fabrication process. This preliminary action simplifies subsequent processing by providing a ready-made framework for integrating different memory cell types without requiring separate through-stack formation for each memory region
Solution Approach 2:
The through-stack structures serve multiple functions simultaneously: they act as word lines for controlling memory cells, provide vertical interconnect pathways for data access, and serve as structural support for the stacked architecture. This multi-functionality reduces the need for additional dedicated structures for each memory type, thereby simplifying the overall fabrication process while maintaining the ability to integrate multiple memory functionalities
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first type through stack structures in a first region of a memory stack, an array of second type through stack structures in a second region of the memory stack, a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures, multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures, and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.