3D Memory Floorplan Architecture for Page Buffer Routing
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to process limitations and high costs, while 3D memory arrays offer increased bit density but require efficient integration of page buffer circuits and bonding structures.
Innovation Solution
A 3D memory architecture with a face-to-face orientation of semiconductor structures, incorporating page buffer circuits and bonding dielectric layers, allows for efficient electrical coupling and reduced routing congestion through strategic alignment and placement of memory planes and page buffer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell scaling to three-dimensional stacked memory structures. Memory cells are arranged in multiple tiers stacked vertically above the substrate, with each tier containing memory cells that access different bit lines. This vertical stacking enables continued memory density improvement without requiring further scaling of individual planar memory cell dimensions, thereby avoiding the associated process complexity and manufacturing cost increases.
2Quantity of substance
If memory cells are stacked vertically to increase bit density, then memory array density is improved, but integration complexity of page buffer circuits increases
Solution Approach 1:
The patent divides the memory structure into distinct segments: memory cell tiers stacked vertically and page buffer circuits positioned in peripheral regions. Each memory tier is associated with specific page buffer circuits that serve dedicated bit line groups. This segmentation allows independent optimization of memory array density while simplifying the integration and routing of page buffer circuits to their corresponding memory tiers.
Solution Approach 2:
The patent positions page buffer circuits in the lateral (horizontal) dimension rather than stacking them vertically with memory cells. This lateral placement in peripheral regions allows efficient electrical coupling to multiple memory tiers through vertical interconnects, reducing routing congestion and integration complexity compared to vertical stacking approaches.
3Productivity
If page buffer circuits are positioned to overlap multiple memory plane boundaries, then routing efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary positioning of page buffer circuits during the semiconductor structure formation process, before final bonding and assembly. The floorplan architecture is established early in manufacturing, with page buffer circuits positioned to optimally serve multiple memory tiers. This preliminary action allows routing optimization to be built into the structure itself, reducing the need for high-precision alignment during subsequent bonding operations.
Data Source
AI summary
A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, wherein the 3D memory array includes a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, wherein each memory plane has a plurality of bit lines oriented in a bit line direction, a memory-plane-boundary, and a fixed location on the first semiconductor structure, each page buffer circuit has a page-buffer-circuit-boundary, the first semiconductor structure and the second semiconductor structure are bonded to each other in a face-to-face orientation, and a first memory-plane-boundary of a first memory plane, and a first page-buffer-circuit-boundary of a first page buffer circuit, are vertically aligned with each other such that a first portion of the first page-buffer-circuit-boundary is offset from the first memory-plane-boundary in the bit line direction so as to be non-overlapping with an area defined by the first memory-plane-boundary.