3D Memory Cell Structure With Thick Gate Layer Etch Stop
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving efficient three-dimensional memory structures with reliable charge storage and easy manufacturing processes.
Innovation Solution
A semiconductor device is designed with a source layer, a stacked body of electrode layers with insulators, a gate layer thicker than the electrode layers, and a charge storage portion between the semiconductor body and the electrode layers, enabling a three-dimensional memory cell array with improved structural integrity and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is implemented with a stacked body including multiple electrode layers, then memory capacity and integration density are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The memory structure is divided into multiple electrode layers (first electrode layer, second electrode layer, third electrode layer) stacked vertically, with each layer serving specific functions. This segmentation allows for modular manufacturing and facilitates the formation of three-dimensional memory cells through sequential processing steps, thereby managing complexity while increasing capacity.
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional stacked structures by adding the vertical dimension with multiple electrode layers. This dimensional change increases memory capacity without proportionally increasing manufacturing complexity, as the stacking approach reuses the same fabrication processes in the vertical direction.
2Manufacturing precision
If a gate layer is made thicker than the electrode layers, then etching control and manufacturing precision are improved, but device area and integration density are reduced
Solution Approach 1:
The gate layer is selectively positioned and dimensioned relative to the electrode layers. The gate layer extends in the first direction and has a thickness greater than the electrode layers in the second direction, creating localized quality differences that provide etching stopper functionality in specific regions while maintaining overall device integration.
Solution Approach 2:
The gate layer serves as an intermediary element between the source layer and the stacked electrode layers. It provides etching control during manufacturing processes and establishes proper electrical connections, acting as a mediator that facilitates precise manufacturing while enabling the three-dimensional structure.
3Reliability
If charge storage portions are positioned between the semiconductor body and electrode layers, then charge storage efficiency is improved, but structural complexity and fabrication steps increase
Solution Approach 1:
The charge storage portions are nested within the three-dimensional structure, positioned between the semiconductor body and the electrode layers. This nesting arrangement integrates charge storage functionality into the existing memory cell structure without requiring separate external storage components, thereby improving efficiency while managing structural complexity.
Solution Approach 2:
The charge storage portions serve multiple functions: they store charge for memory operation, define the boundaries of memory cells, and facilitate electrical connections between layers. This multi-functionality reduces the need for additional dedicated structures, balancing charge storage efficiency with structural simplicity.
4Reliability
If the semiconductor body extends through the stacked body and gate layer with side wall contact, then electrical connection and charge transport are improved, but manufacturing precision requirements increase
Solution Approach 1:
The semiconductor body is formed to extend through the stacked body and gate layer with its side wall positioned to contact the source layer before final assembly steps. This preliminary positioning ensures proper electrical connection pathways are established early in the manufacturing process, facilitating subsequent alignment and reducing precision requirements for later steps.
Data Source
AI summary
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.