3D Semiconductor Memory Gate Electrode Fabrication
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Solution Overview
Problem
Conventional three-dimensional semiconductor memory devices face limitations in integration density and reliability due to expensive equipment and complex fabrication processes, leading to unstable processing and low product reliability.
Innovation Solution
A method of fabricating a three-dimensional semiconductor memory device by alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming active patterns, and using an isotropic etch process to create gate electrodes, which are separated and recessed, enhancing process margins and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional semiconductor memory devices are fabricated using existing methods, then integration density can be improved, but processing stability and product reliability deteriorate due to complex fabrication processes
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming sacrificial layers and insulating layers alternately, creating active patterns, forming trenches, removing sacrificial layers to create recess regions, forming information storage layers, and forming gate electrodes through isotropic etching. This segmentation allows each step to be optimized independently, improving both integration density and processing stability.
Solution Approach 2:
Sacrificial layers are formed in advance before the final gate electrode structure is created. These sacrificial layers (such as oxide or nitride layers) serve as placeholders that define the future gate electrode positions and shapes. The preliminary formation of these layers enables precise control over the final device geometry while simplifying the overall fabrication process.
2Area of stationary object
If pattern miniaturization is pursued to increase integration density, then area occupied by unit memory cell is reduced, but manufacturing cost increases due to expensive semiconductor equipment
Solution Approach 1:
The invention transitions from two-dimensional planar memory cells to three-dimensional vertical structures by stacking multiple layers of sacrificial and insulating layers alternately. This vertical stacking approach increases integration density without requiring further miniaturization of the lateral dimensions, thereby avoiding the need for expensive advanced lithography equipment while achieving higher capacity.
3Device complexity
If conventional fabrication processes are used for three-dimensional semiconductor memory devices, then device structure can be formed, but processing stability deteriorates due to unstable processing
Solution Approach 1:
The invention employs an isotropic etch process with controlled etching parameters to form gate electrodes. By carefully controlling the etching conditions (such as etchant composition, temperature, and time), the process achieves high precision in forming the gate electrode structures while maintaining stability and repeatability. The etching parameters are optimized to ensure consistent results across different manufacturing batches.
4Manufacturing precision
If gate electrodes are formed to be separated and recessed, then process margin is enhanced, but manufacturing complexity increases
Solution Approach 1:
Sacrificial layers serve as intermediary structures that temporarily occupy the space where gate electrodes will eventually be formed. These intermediary layers simplify the manufacturing process by providing a clear template for gate electrode formation. After the gate electrodes are formed using the isotropic etch process, the sacrificial layers are removed, leaving the desired separated and recessed gate electrode structure with enhanced process margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density and superior reliability in semiconductor memory devices by optimizing the fabrication process, reducing equipment costs, and minimizing etch damage to other structures.
Implementation Method 1
performing an isotropic etch process with respect to the gate conductive layer having the empty region to form gate electrodes
Data Source
AI summary
A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.