Solid-State Devices TRIZ Cases

Triple patterning creates recolorable metal features to resolve color conflicts and design rule violations in dense 10nm standard cell layouts.

A thin-film transistor substrate design increases storage capacitor capacitance using a silicon oxide dielectric layer to shrink the component footprint.

Patterned conductive layers replace bulky golden balls to transmit signals, reducing thickness and border width.

Phosphor wavelength conversion boosts luminous flux by 130% while managing radiation power trade-offs.

Address rewrite modules dynamically adjust chip addresses to resolve pin count limitations and maximize storage capacity in multi-chip packages.

Nanoparticles in thin films scatter emitted light to reduce total reflection and boost display luminance.

Direct optical coupling on rigid PCBs eliminates flexible waveguides, reducing signal loss and alignment complexity.

A light emitting device package positions a second pad laterally adjacent to through-holes to ensure electrical spacing from the first insulation layer.

A photodetector uses an inversion zone generator to create tunable zones within a semiconductor substrate for selective charge carrier collection.

A substrate with segmented insulating films changes refractive index at specific interfaces to enhance light emission characteristics.

Segmented variable resistance memory cells use stacked transition metal oxide patterns to achieve consistent electrical characteristics across dense arrays.

Segmenting gate oxide annealing on a sacrificial substrate protects temperature-sensitive polymer materials from degradation during JFET production.

Multi-tone masking reduces mask count and exposure times to lower manufacturing costs.

Heterocycle host and iridium guest emission layer structure improves sublimability and heat stability for high efficiency OLEDs

Non-flat pixel structures in curved regions correct reddish or bluish tinting by balancing light emission through reflective electrodes.

A dual-host emission layer forms an exciplex to resolve singlet exciton inactivation, extending device life while maintaining high emission efficiency.

A dual-port SRAM design adjusts bit line interconnection lengths to balance junction capacitances across read and write ports.

Relocating the plug connecting a photodiode and transfer transistor away from shallow trench isolation regions reduces current leakage in CMOS image sensors.

A vertical organic light-emitting transistor uses a source insulation film to cover the electrode and control charge injection.

A segmented fabrication method protects memory gates using distinct material layers to maintain spacer integrity during processing.

Pre-selecting core batches with Stokes shift under 13 nm resolves emission width inconsistency and boosts quantum yield.

Indium doping creates a lateral gradient that lowers barrier potential, enabling complete charge transfer and minimizing image lag artifacts.

Segmented ceramic substrates resolve the heat dissipation versus mechanical strength trade-off in LED modules.

Repellent surface treatment condenses evaporating droplets into thicker solid dots, eliminating measurement errors caused by low solid matter concentration.

A pixel structure divides electrode domains into bar-like segments and places signal lines in a separate layer to enhance display efficiency.

Ion implantation creates a lateral electric field that removes residual FET-channel charge, resolving noise and dynamic range limitations in CMOS imagers.

An OLED display panel incorporates an organic material layer within the hole forming area to reduce height differences between regions.

Segmented optical filter films on a lithography mask alternate frequency ranges to reduce edge interference and achieve finer patterns.

A soft X-ray detection unit layout positions amplifier transistors to minimize charge discharge regions, ensuring accurate energy measurement.

An OLED manufacturing method charges pixel electrodes to form an electric field that directs ionized evaporation material for precise deposition.

Vertical stacking of gate patterns increases integration density while spaced string drain regions prevent dopant interference.

A semiconductor device uses a zigzag supporting structure to enhance stack integrity.

Laser energy passes through a mounting tape to modify the non-active region of a semiconductor wafer, eliminating debris from mechanical saw blades.

Periodic vibration prevents nozzle deposition while maintaining high evaporation efficiency and particle consistency.

A light-emitting device adjusts conductive portion density across semiconductor regions to enhance current distribution.

Sacrificial patterns define contact holes using gate and molding masks, improving process margin and yield.

T-shaped electrodes with gold-filled grooves prevent humid air permeation and improve heat dissipation for longer LED lifespan.

Rugged surfaces enable optical detection of fabrication failures like reflow without adding complex functional layers.

Strained AlN, AlGaN, and GaN buffer layers balance tensile and compressive stresses to minimize bowing and cracking in GaN thin films on silicon substrates.

An inorganic photoluminescent layer converts ultraviolet excitation into narrow-band visible light, improving color purity and stability against moisture.

Sacrificial lift-off patterns bypass exposure limits to form narrow electrodes, increasing aperture ratio and transmittance.

Direct edge bonding of a flexible film eliminates large outer lead bonding areas, reducing border width while maintaining connection reliability.

Back exposure and halftone masks reduce photomask steps from six to four, lowering costs while protecting the metal oxide channel layer.

Segmenting the memory array into blocks with dedicated driver circuits reduces non-selected current flow and decoder complexity.

A polarizing plate uses a substrate film with in-plane phase difference Re of 20 nm or less to serve as its protective layer.

Dielectric pillars prevent stack collapse during manufacturing by providing mechanical support between the substrate and alternating layers.

Two access transistors per cell reduce PCRAM layout area by 37% while maintaining high set and reset current handling capacity.

Isotropic etching creates separated gate electrodes in 3D memory devices, resolving reliability issues caused by complex conventional processes.

Differentiated impurity regions in a hybrid pipe gate prevent charge trapping, maintaining stable threshold voltage and cell current.

Laser-formed boundary trenches in a composite film enable fluorine-based gas plasma etching, eliminating vacuum chamber contamination from resist ashing.