Hybrid Pipe Gate Structure for 3D NAND Memory
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Solution Overview
Problem
In 3D non-volatile memory devices, the use of N-type poly silicon gates with small work function leads to charge trapping in the gate insulating layer during erase operations, increasing threshold voltage and reducing cell current, thereby deteriorating memory device characteristics.
Innovation Solution
A semiconductor device with a hybrid-type pipe gate structure, where a region with a first-type impurity contacts the pipe channel layer and the remaining regions have a second-type impurity, preventing charge trapping and maintaining optimal threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If N-type poly silicon gate is used, then work function is small, but charge trapping occurs in gate insulating layer during erase operation
Solution Approach 1:
The pipe gate is divided into two regions with different impurity types: a first region contacting the pipe channel layer with first-type impurity and remaining second regions with second-type impurity. This local differentiation allows the gate to have different work functions in different regions, preventing charge trapping while maintaining appropriate energy characteristics for device operation.
2Reliability
If charge is trapped in gate insulating layer, then threshold voltage increases, but cell current decreases
Solution Approach 1:
By implementing a hybrid-type pipe gate with different impurity types in different regions, the gate structure prevents charge trapping in the gate insulating layer. This maintains stable threshold voltage while preserving adequate cell current flow through the pipe channel layer, resolving the trade-off between voltage stability and current performance.
3Ease of manufacture
If uniform impurity distribution is used in pipe gate, then manufacturing is simple, but charge trapping occurs and device characteristics deteriorate
Solution Approach 1:
The pipe gate employs a hybrid-type impurity distribution where a first region contains first-type impurity and remaining second regions contain second-type impurity. This localized differentiation improves device characteristics by preventing charge trapping while maintaining manufacturability through established semiconductor fabrication techniques for creating doped regions.
Data Source
AI summary
A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.