TFT Substrate Storage Capacitor Area Reduction
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Solution Overview
Problem
In thin-film transistor (TFT) substrates for liquid crystal displays, reducing the area of the storage capacitor section while maintaining reliability and preventing electrostatic vulnerability, as excessive reduction in gate insulation layer thickness or using a double-layered SiO2 and SiNx structure can deteriorate the TFT.
Innovation Solution
A TFT substrate design with a gate wiring, capacitor dielectric layer, gate insulation layer, active pattern, data wiring, protection layer, and pixel electrode, where the capacitor dielectric layer is formed with silicon oxide to increase capacitance and reduce the storage capacitor section area, and the gate insulation layer is thicker than the capacitor dielectric layer to enhance reliability, with a method involving a patterning process using one mask to form the gate wiring and capacitor dielectric layer simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the thickness of the gate insulation layer is reduced to decrease the storage capacitor section area, then the aperture ratio is improved, but the reliability of the gate insulation layer deteriorates and it becomes vulnerable to electrostatic charges
Solution Approach 1:
The gate insulation layer is divided into multiple sub-layers (first gate insulation layer and second gate insulation layer) with different thicknesses and materials. The first layer provides electrostatic protection while the second layer ensures electrical insulation, resolving the contradiction between thinning for area reduction and maintaining reliability.
Solution Approach 2:
The gate insulation layer uses a composite structure combining different insulating materials (such as silicon oxide and silicon nitride) with different properties. This composite approach allows the layer to simultaneously provide electrostatic charge resistance and electrical insulation, enabling area reduction without compromising reliability.
2Area of stationary object
If a double-layered structure of SiO2 and SiNx is used to reduce storage capacitor area, then the capacitance increases, but SiO2 remaining under the channel deteriorates the TFT
Solution Approach 1:
The problematic SiO2 layer is extracted or removed from beneath the TFT channel region. The gate insulation layer is configured so that only the necessary insulating layers remain under the channel, eliminating the harmful SiO2 accumulation while maintaining the storage capacitor function in other areas.
Solution Approach 2:
The gate insulation layer has different compositions and thicknesses in different regions. Under the TFT channel, the layer is optimized to prevent SiO2 accumulation and protect TFT characteristics, while in the storage capacitor region, the structure is optimized for capacitance enhancement, thus resolving the local quality conflict.
3Device complexity
If the gate insulation layer is made thinner to reduce manufacturing complexity, then the manufacturing process is simplified, but the electrostatic protection capability is reduced
Solution Approach 1:
The gate insulation function is segmented into multiple layers with specialized roles. One layer is specifically designed for electrostatic protection with appropriate thickness and material properties, while other layers handle electrical insulation, thus maintaining protection capability without excessive overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the aperture ratio by increasing the capacitance of the storage capacitor section without deteriorating the TFT characteristics, reducing the storage capacitor section area, and simplifying the manufacturing process by self-aligning the capacitor dielectric layer on the lower storage electrode.
Implementation Method 1
the capacitor dielectric layer is formed with silicon oxide to increase capacitance
Implementation Method 2
the capacitor dielectric layer is formed with silicon oxide to increase capacitance
Data Source
AI summary
A thin-film transistor substrate includes a gate line, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data line, a protection layer, and a pixel electrode. The gate wiring including a gate electrode, a lower storage electrode, and a gate metal pad is disposed on a substrate. The capacitor dielectric layer is disposed on the lower storage electrode and the gate insulation layer is disposed on the substrate. The active pattern includes an active layer and a dummy active layer disposed on the gate insulation layer in a gate electrode region and a gate metal pad region, respectively. A portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through a first contact hole in the gate insulation layer.