Low-Temperature JFET Transistor Fabrication via Substrate Segmentation
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Solution Overview
Problem
The production of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) requires high-temperature annealing, which is incompatible with substrates that cannot withstand high temperatures, such as those with electronic components or polymer materials that degrade at temperatures above 100°C.
Innovation Solution
A method for producing JFET transistors on a substrate that involves creating a stack of doped semiconductor layers, securing it to a second substrate, and etching to form the transistor structures without exposing the second substrate to high temperatures, allowing for the production of N- or P-type transistors compatible with low-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing is performed to grow gate oxide for MOSFETs, then satisfactory dielectric properties are achieved, but substrates with temperature-sensitive materials (polymers, metal interconnection layers) degrade or become incompatible
Solution Approach 1:
The patent divides the transistor structure into separate segments: the gate electrode and gate oxide are formed on a first substrate, while the channel layer is formed on a second substrate. This segmentation allows the gate oxide to be annealed at high temperature on the first substrate without exposing the temperature-sensitive second substrate to harmful heat, thus resolving the contradiction between achieving satisfactory dielectric properties and preventing substrate degradation
Solution Approach 2:
The patent introduces an intermediary approach by forming the gate oxide and gate electrode as separate components that can be prepared independently. The gate oxide is grown and annealed on a sacrificial or separate substrate structure, then the gate electrode is formed, and finally the channel layer is deposited on the final substrate. This intermediary separation allows high-temperature processing to be isolated from temperature-sensitive materials
2Reliability
If high-temperature processing is used for MOSFET production, then reliable transistor performance is achieved, but the process becomes incompatible with low-temperature substrates and materials
Solution Approach 1:
The patent segments the transistor fabrication process into distinct stages on different substrates: gate oxide formation and annealing on a first substrate, gate electrode formation, and channel layer deposition on a second substrate. This segmentation enables high-temperature processing only where needed for reliable transistor performance while maintaining compatibility with temperature-sensitive substrates for the channel layer
Solution Approach 2:
The patent transitions from a single-substrate vertical integration approach to a multi-substrate layered architecture. By stacking the gate structure on one substrate and the channel on another, then bonding them together, the patent adds a dimensional aspect to the fabrication process that allows independent temperature optimization for each layer, thereby improving both reliability and substrate compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of transistors on substrates that cannot tolerate high temperatures, preserving the integrity of electronic components and materials, and facilitating the creation of 3D monolithic circuits using a 'cold' process, without degrading the substrate during transistor production.
Implementation Method 1
The first layer is produced by epitaxy on the first substrate
Implementation Method 2
The first layer comprises a first semiconductor doped according to a first conductivity type, and a second layer comprises a second semiconductor doped according to a second conductivity type
Data Source
AI summary
Method for producing a JFET transistor, comprising:a) producing, on a first substrate, a stack comprising a first layer comprising a first semiconductor doped according to a first conductivity type and a second layer comprising a second semiconductor doped according to a second conductivity type, the first layer being disposed between the first substrate and the second substrate, thenb) securing the stack against a second substrate such that the stack is disposed between the first substrate and the second substrate, thenc) removing the first substrate, thend) etching the first layer such that a remaining portion of the first layer forms a front gate of the first JFET transistor, thene) etching the second layer such that a remaining portion of the second layer is disposed below the front gate of the first JFET transistor and forms the channel, the source and the drain of the JFET transistor.