Multi-chip Package Address Rewiring for SSD Capacity
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Solution Overview
Problem
Current SSDs face limitations in maximizing capacity due to a limited pin count and assembly area for the transfer controller, which restricts the flexibility of memory systems, especially in configuring multi-chip packages with multiple laminated memory chips.
Innovation Solution
A multi-chip package design that includes a first group of memory chips with internal wiring systems to couple memory chips to terminals receiving chip-enable signals, allowing for flexible connection configurations through common signal line groups and address rewriting modules, enabling independent operation of multiple memory chips within the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple laminated memory chips are used to maximize capacity, then storage capacity is improved, but pin count and assembly area limitations prevent flexible configuration
Solution Approach 1:
The patent divides the memory chip group into multiple sub-groups, where each sub-group can be independently controlled through separate internal wiring systems. This segmentation allows different connection configurations (first connection example with common signal lines, second connection example with separate signal lines) within the same multi-chip package, resolving the contradiction between high capacity and configuration flexibility.
2Productivity
If memory chips are commonly connected to maximize capacity utilization, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs address rewrite modules that can dynamically rewrite chip addresses stored in memory regions based on detection results. This dynamic address rewriting allows the system to adapt to different connection configurations (common or separate signal lines) without requiring precise manufacturing differentiation, thereby maintaining high productivity while reducing manufacturing precision requirements.
3Reliability
If specific manufacturing is done for each connection example to ensure reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal multi-chip package structure that can accommodate multiple connection configurations (first connection example with common signal line groups, second connection example with separate signal line groups) through the same basic architecture. The address rewrite modules and detection mechanisms enable the same hardware design to reliably support different configurations, achieving high reliability without increasing manufacturing complexity.
Data Source
AI summary
A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.