3D Memory Array Shared Gate Electrode Driver Circuit
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Solution Overview
Problem
In large capacity memory arrays, connecting multiple word lines to a single driver circuit results in increased chip area due to non-selected current flow and the need for numerous decoder circuits and wirings, leading to larger chip sizes.
Innovation Solution
A miniaturized storage device with a three-dimensional memory cell array and a selective word line driver circuit that reduces non-selected current flow by using a shared gate electrode and select transistors to connect global word lines and bit lines, allowing for a smaller chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple word lines are connected to a single word line driver circuit, then the number of driver circuits is reduced, but non-selected current flows in non-selected memory cells causing the driver circuit area to increase
Solution Approach 1:
The patent segments the memory cell array into multiple blocks along the column direction, with each block having its own dedicated word line driver circuit. This segmentation prevents non-selected current from affecting other blocks, as each block is independently controlled. The segmentation allows multiple driver circuits to share the same bit line while maintaining electrical isolation between blocks through the block selection mechanism.
Solution Approach 2:
The patent introduces select transistors as intermediary elements between the word line driver circuits and the memory cells. These select transistors act as switches that are controlled by select lines to enable or disable current flow to specific blocks. This intermediary mechanism allows the driver circuits to be shared across multiple blocks while preventing unwanted current flow through non-selected blocks.
2Device complexity
If many word lines are connected to one word line driver circuit, then driver circuit count is reduced, but decoder circuits and wirings increase chip area
Solution Approach 1:
The memory array is segmented into multiple blocks that can be independently selected and activated. Each block contains a subset of word lines that are controlled by the same shared driver circuit. This segmentation reduces the need for extensive decoder circuits because block selection is achieved through a combination of block select signals and word line select signals within each block, rather than requiring individual decoding for every word line.
Solution Approach 2:
The word line driver circuits are designed to be universal and multi-functional, serving multiple blocks simultaneously. The same driver circuit can drive word lines in different blocks by receiving control signals that activate the appropriate select transistors for the desired block. This universality eliminates the need for separate dedicated driver circuits for each block, reducing overall chip area while maintaining full functionality.
3Reliability
If block selection is performed by applying voltage to both bit line and word line simultaneously, then selection is achieved, but voltage application complexity increases
Solution Approach 1:
The patent implements preliminary action by first selecting the desired block through the block select transistors before activating the word line driver circuit. The select lines are activated in advance to prepare the block for operation, establishing the correct electrical state before the actual word line selection and data operation occur. This preliminary block selection simplifies the subsequent voltage application sequence and reduces control complexity.
Solution Approach 2:
The patent employs dynamic control of voltage application through time-multiplexed operation. Different voltage levels and patterns are applied at different times during the memory operation cycle. Block select signals are applied first to activate the appropriate block, followed by word line select signals, and then the actual data write or read voltages. This dynamic, sequential approach to voltage application simplifies control logic compared to simultaneous multi-voltage application.
Data Source
AI summary
A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.