Variable Resistance Memory Device Uniformity via Segmented Stacking
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Solution Overview
Problem
Existing semiconductor devices with variable resistance memory technology face challenges in achieving uniform electrical characteristics across memory cells, leading to inconsistent performance.
Innovation Solution
The solution involves a variable resistance memory device design with upper and lower memory cells having uniform electrical characteristics, featuring a specific stacking of conductive lines, variable resistance structures, and sacrificial patterns, along with buffer and capping patterns, all made from transition metal oxides, to ensure consistent electrical properties across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If variable resistance memory devices are highly integrated with crossing-point array structure, then device density and integration level are improved, but manufacturing precision and uniformity of electrical characteristics deteriorate
Solution Approach 1:
The memory device is divided into upper and lower memory cells with separate variable resistance structures, each having independent first and second variable resistance patterns. This segmentation allows independent optimization and control of each cell's electrical characteristics, improving uniformity while maintaining high density through the crossing-point array architecture.
Solution Approach 2:
Different variable resistance patterns (first, second, third, fourth) are formed with specific local properties using transition metal oxides. Each pattern can be independently tailored with controlled thickness, composition, and oxygen content to achieve desired electrical characteristics locally, ensuring uniformity across all memory cells in the highly integrated device.
2Adaptability or versatility
If multiple variable resistance patterns are stacked in the same memory cell, then device functionality and storage capacity are improved, but device complexity increases
Solution Approach 1:
Multiple variable resistance patterns are nested within each memory cell structure, with first and second patterns in upper cells and third and fourth patterns in lower cells. This nesting approach allows multiple storage functions within a unified structural framework, increasing storage capacity while managing complexity through systematic repetition of the same structural motif.
Solution Approach 2:
The same basic structural template (electrodes, switching element, variable resistance patterns) serves multiple functions across upper and lower memory cells. This universal design allows the same fabrication processes to be applied repeatedly, managing complexity through standardization while achieving enhanced storage capacity through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves consistent electrical characteristics across memory cells, enhancing the performance and reliability of semiconductor devices by ensuring uniformity in resistance patterns and material properties.
Implementation Method 1
the first buffer pattern may absorb oxygen from the first and second variable resistance patterns or may supply oxygen thereto
Data Source
AI summary
A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.