3D Nonvolatile Memory Gate Insulating Layer Back Tunneling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3-D nonvolatile memory devices face issues with insufficient thickness of the tunnel insulating, charge trap, and charge blocking layers, leading to threshold voltage rise during erase operations and read disturbance due to electron back tunneling.
Innovation Solution
Incorporating a first and second gate insulating layer with a multi-layered stack structure, including a nitride and oxide layer, between the pipe gate and memory layers to provide sufficient thickness and prevent electron back tunneling, along with a method of manufacturing involving etching, sacrificial layers, and oxidization processes to form the gate insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the tunnel insulating layer, charge trap layer, and charge blocking layer are used as the gate insulating layer of the pipe gate, then the device structure is simplified, but the gate insulating layer thickness is insufficient causing electron back tunneling
Solution Approach 1:
The gate insulating layer is segmented into multiple distinct layers: a first gate insulating layer (thickness 50-150 nm) and a second gate insulating layer (thickness 2-5 nm). This segmentation provides sufficient total thickness to prevent electron back tunneling while maintaining structural organization and functional differentiation between the layers.
Solution Approach 2:
The gate insulating layer uses composite material structure combining different dielectric materials with complementary properties. The first gate insulating layer uses materials with high breakdown voltage (such as oxide layers), while the second gate insulating layer uses materials optimized for interface quality and thin-film properties (such as nitride layers), creating a composite structure that achieves both thickness and performance requirements.
2Reliability
If the gate insulating layer thickness is increased to prevent back tunneling, then threshold voltage stability improves, but device manufacturing complexity increases
Solution Approach 1:
The invention optimizes specific parameter ranges for each gate insulating layer: the first gate insulating layer is designed with thickness of 50-150 nm and the second with 2-5 nm. These parameter specifications balance the need for sufficient total thickness to prevent back tunneling with manufacturing feasibility, ensuring reliable threshold voltage control without excessive complexity.
3Reliability
If a multi-layered gate insulating layer structure is implemented, then electron back tunneling is prevented, but manufacturing process complexity increases
Solution Approach 1:
The first gate insulating layer is formed preliminarily before the memory layer deposition, establishing a thick base layer that prevents back tunneling. Subsequently, the second gate insulating layer is formed to complete the interface with the memory layer. This preliminary action sequence simplifies manufacturing by breaking down the complex multi-layer formation into manageable sequential steps.
Solution Approach 2:
Different regions of the gate insulating structure have locally optimized properties: the first gate insulating layer provides bulk insulation with high breakdown voltage, while the second gate insulating layer provides interface quality optimized for the memory layer contact. This local quality differentiation achieves reliable electron blocking without requiring uniform thickness or material properties throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents threshold voltage rise and shift in memory cell voltages by ensuring a sufficient gate insulating layer thickness, enhancing the reliability of the 3-D nonvolatile memory device.
Implementation Method 1
a first gate insulating layer interposed between the first pipe gate layer and the memory layer... having a sufficient thickness to prevent back tunneling of electrons
Implementation Method 2
a method of manufacturing involving etching, sacrificial layers, and oxidization processes to form the gate insulating layers
Data Source
AI summary
A three dimensional (3-D) nonvolatile memory device includes a first pipe gate layer, a second pipe gate disposed over the first pipe gate layer, word lines formed over the second pipe gate layer, memory channel layers configured to penetrate the word lines, a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with the bottom surface of the second pipe gate layer and couple the lower ends of the memory channel layers, a memory layer configured to surround the pipe channel layer and the memory channel layers, and a first gate insulating layer interposed between the first pipe gate layer and the memory layer.