3D Memory Gate Line Structure for Overlay-Tolerant Channel Plug Protection
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Solution Overview
Problem
The manufacturing of high-density 3D memory devices faces challenges such as overlay issues due to the increase in depth, which complicates the formation of channel and gate line holes, leading to increased fabrication costs and reduced product yield.
Innovation Solution
The design of a semiconductor device with a gate line structure where the top portion is positioned higher than the channel plug, allowing for a dielectric layer to protect the channel plug without needing a separate protection film process, thereby resolving overlay issues and enlarging the processing window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the depth of 3D memory device increases to achieve high density, then memory capacity increases, but overlay issues worsen and manufacturing precision deteriorates
Solution Approach 1:
The gate line structure transitions from a traditional planar configuration to a three-dimensional structure with a top portion extending above the channel plug. This vertical dimensionality change allows the gate line to maintain proper electrical connection while accommodating the increased device depth, thereby resolving overlay issues that arise in high-density 3D memory devices.
Solution Approach 2:
The dielectric layer is deposited to expose the channel plug before subsequent processing steps. This preliminary action protects the channel plug from damage during later fabrication steps and eliminates the need for separate protection films, thereby improving manufacturing precision and reducing overlay errors.
2Ease of manufacture
If traditional gate line structure is used, then fabrication process is simpler, but separate protection film process is needed increasing device complexity
Solution Approach 1:
The gate line structure is merged with the dielectric layer formation process. The dielectric layer is deposited as part of the gate line structure fabrication, simultaneously providing electrical isolation and protection for the channel plug. This merging eliminates the need for separate protection film processes, reducing device complexity while maintaining ease of manufacture.
Solution Approach 2:
The dielectric layer serves multiple functions: it provides electrical isolation for the gate line, protects the channel plug from damage, and maintains structural integrity. This multi-functionality reduces the number of separate components and processes needed, thereby simplifying the overall fabrication process while reducing device complexity.
3Reliability
If separate protection film process is added, then channel plug protection is improved, but fabrication cost increases and productivity decreases
Solution Approach 1:
The protection function is merged into the dielectric layer deposition process. The same dielectric material that provides gate line isolation also serves as the protection film for the channel plug. This eliminates redundant process steps, maintaining channel plug protection while improving fabrication efficiency and productivity.
Solution Approach 2:
The separate protection film process is extracted and eliminated from the fabrication sequence. The protective function is integrated into the existing dielectric layer formation, removing the need for additional deposition, patterning, and removal steps, thereby reducing fabrication cost and improving productivity.
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for gate line structures in semiconductor devices. An example semiconductor device includes a semiconductor structure including a stack of alternating conductive layers and isolating layers. The semiconductor device further includes channel structures extending through the stack along a first direction. The channel structures include at least a first channel structure that has a top end and a bottom end along the first direction. The first channel structure includes a channel plug at the top end. The semiconductor device further includes a gate line structure extending through the stack along the first direction. The gate line structure includes a top portion and a body portion arranged along the first direction. The top portion of the gate line structure is farther away from the bottom end of the first channel structure than the channel plug along the first direction.