3D Memory Cell Structure With Graded Dopant Regions
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of fine pattern forming technology, making three-dimensional semiconductor memory devices necessary for higher integration and cost-effective manufacturing.
Innovation Solution
A semiconductor memory device with a three-dimensional structure featuring word lines, channel patterns, bit lines, and data storage elements, including dopant regions of varying concentrations, is designed to enhance integration without relying on expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited by the area occupied by a unit memory cell and requires expensive fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction (third direction perpendicular to the substrate), enabling higher integration density without requiring finer lateral patterning. This dimensional change allows integration to be determined by vertical stacking rather than lateral pattern fineness.
2Productivity
If pattern fineness is increased to improve integration, then unit memory cell area is reduced, but expensive process equipment is required
Solution Approach 1:
By stacking memory cells vertically, the patent reduces dependence on lateral pattern fineness. The integration density is improved through increased stacking height rather than decreased cell footprint, avoiding the need for expensive fine pattern forming equipment.
Solution Approach 2:
The patent introduces dopant regions with different concentrations (first dopant region with first concentration, second dopant region with second concentration) at different locations within the channel structure. This local differentiation of dopant concentration optimizes device performance in specific regions without requiring uniform high-precision patterning across the entire structure.
3Productivity
If three-dimensional vertically stacked memory cells are implemented, then integration density is improved, but device structure becomes more complex
Solution Approach 1:
The three-dimensional memory structure is segmented into repeating units, each comprising a channel pattern, word line, bit line, and data storage element. These modular units are stacked vertically, allowing the complex 3D structure to be built from standardized building blocks, which simplifies fabrication and design.
Solution Approach 2:
The channel pattern serves multiple functions: it provides the conduction path for current flow, defines the active region for charge storage, and structures the dopant regions. The vertical stacking approach makes the same structural elements serve both as individual cell components and as part of the overall three-dimensional integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure allows for increased integration and efficient manufacturing of semiconductor memory devices, overcoming the limitations of two-dimensional devices by optimizing the use of dopant regions and gate structures.
Implementation Method 1
Each of the channel patterns may include a first dopant region adjacent to the bit lines, a second dopant region adjacent to the data storage elements, and a channel region provided between the first and second dopant regions
Data Source
AI summary
A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.