Digital Storage TRIZ Cases

Parallel NFET and PFET branches route program and erase voltages in RRAM while keeping low-voltage devices within SOA to cut leakage.

Interleaved booster cells reconfigure PMOS and NMOS connections to speed word-line rise and limit parasitic effects in memory arrays.

Gap-bridged closed-loop magnetic conductors let domain walls cross spiral sections, expanding counting range without larger chip area or higher defect risk.

A boosting circuit detects core-voltage drops during mismatch compensation and supports sensing to preserve margin and prevent malfunctions.

A bismuth-metal SOT layer keeps a high spin Hall angle while withstanding 400°C BEOL annealing for stable MRAM switching.

By scanning only high-error word lines, the memory system detects read disturb risk and triggers refresh with less host blocking.

Multiple write drivers and overlapping column select paths enable multi-word row writes in fewer clock cycles, increasing memory write throughput.

Selective series resistors and parallel switches cut hold current in memory cell lines to prevent read-write failures and oscillation.

A dielectric interfacial layer in SOT MRAM boosts spin polarization, lowers programming current, and protects tunnel-layer reliability.

Selective power-amplifier shutdown keeps inactive non-rank0 DRAM logic non-floating, cutting leakage current and stack power waste.

Nano-pores in the MTJ free layer cut saturation magnetization without thinning or added elements, reducing write errors and magnetic interference.

CMOS transmission-gate selection boosts write current in resistive memory cells while lowering power use and improving cell uniformity.

Pre-verify logic applies inhibition voltage only to selected memory cells, limiting over-programming and narrowing threshold voltage distribution.

A dual-gate read transistor in a stacked 3D memory array cuts read word line IR drop, enabling longer lines, smaller cells, and higher capacity.

Pre-setting a negative well voltage lets the decoder switch underdrive onto the word line faster, improving memory word line setting.

An amorphous metal oxide, blocking, and buffer stack suppresses oxygen diffusion and crystal transfer to stabilize MTJ resistance and switching at high temperature.

Independent currents in three conductor layers generate spin orbit torque to write magnetoresistance states without direct element current.

Replica-cell tracking generates reference voltages to offset PVT variation in ReRAM crossbars, cutting read-bit errors in multi-bit reads.

Discontinuous stable interface layers and multi-component electrodes help scaled RRAM lower forming voltage and current while stabilizing filament growth.

Separate bias control for memory cells and peripheral circuits cuts leakage current and improves reliability across changing conditions.

Bank-specific CDC buffers let fast compute engines access slower SRAM banks with lower latency, better bandwidth use, and less power.

An antiferromagnetic storage layer with reversible Hall coefficient improves write speed and data stability while limiting crystallinity variation.

Holding portions store transistor currents so product-sum operations use less power and stay more stable against temperature and device variation.

Vertical memory cells use graded dopant regions near the channel to raise integration density without relying on costly fine patterning.

A pipelined CAM-based cumulative distribution table sampler cuts latency, energy, and area while suppressing timing and power side-channel leakage.

Symmetrical arrays and dual current comparison offset bit-line leakage, keeping memory read windows accurate across temperatures.

A vertical MOSFET with SiGe source/drain shrinks memory cell area while improving read/write behavior, contact resistance, and floating body control.

A hybrid sense amplifier layout shares amplifiers across banks while adding bank-specific paths to curb usage-based disturbance and command conflicts.

Separating bit lines and complementary bit lines into different tracks cuts 4Cpp SRAM metal congestion and avoids fin cuts and shared contacts.

Separate write-data wiring pairs by memory bank group to cut RC loading, reduce signal distortion, and speed writes.

Bit-line precharge and column multiplexing improve pseudo dual-port SRAM speed and signal stability without enlarging memory cells.

Separate clock-tree alignment and per-device tuning reduce skew on command/address buses, improving memory read/write accuracy.

Multiple-phase data clocks and delayed test-pattern training tune duty cycle settings to maintain read margins across voltage, temperature, and high-frequency shifts.

Voltage-aware read and write assist control lets SRAM macros adapt across DVFS ranges, reducing power loss and data destruction risk.

Separating array power-up from bit line pre-charge with a secondary sleep loop reduces memory wake-up peak current by up to 42%.

Multiple ferroelectric capacitors store duplicate data in each cell, cutting write-back after destructive reads to improve density, latency, and endurance.

An HfO2 interfacial layer boosts remnant polarization in thin hafnium-based ferroelectric films while reducing leakage current for scaled memory devices.

Swap commands and addresses let a memory chip set swap mode without a separate pin, reducing PCB wiring interference and preserving signal integrity.

Multiple enable pulses on one wordline let pseudo multi-port memory raise read throughput while avoiding four-port SRAM cost and area.

Hybrid offset compensation tunes N-type and P-type sense amplifiers to improve DRAM sensing accuracy under PVT variation.

An inverted T-shaped bottom electrode concentrates the electric field at its tip, accelerating filament formation and RRAM programming.

Preallocated redundancy units and nonvolatile mapping let volatile memory replace failed units faster while preserving remap data after power loss.

A two-phase fluid loop uses assisted condensation to control semiconductor temperature and pressure while reducing thermal stress during testing.

Multi-step column select signals compensate line resistance and capacitance, improving access to distant memory cells.

Selective bit line clamping cuts DC current in unselected TDP memory columns, improving electromigration compliance and read-mode power use.

Paired selector-only memory cells written with opposite polarities enable differential reads that offset Vth drift and preserve data integrity over time.

Photon avalanche carrier trapping in a PN-junction waveguide enables non-volatile optical storage on PICs while reducing OEO conversions.

Integrating MRAM with a magnetic-core inductor on one chip cuts off-chip assembly, reducing thickness and manufacturing cost.

Initialization-stage training uses oscillator codes to correct clock-data timing drift from voltage and temperature changes with less startup overhead.

Shared word line pads and vertically stacked memory cells cut pad-region area and raise semiconductor memory integration density.

A dual in-line memory module operates across multiple data channels to enable flexible single or dual channel configurations.

Direct top electrode coupling to the overlying metal layer eliminates intermediate vias, reducing overall height for back-end-of-line process compatibility.

Latching predecoder circuitry resolves address combinations early in the clock cycle, eliminating detection delays caused by relying on delayed clock signals.

A two-level multiplexing apparatus connects local memory banks to global bit lines using selective input forwarding.

Time-sharing inter-chip wiring connects multiple semiconductor chips simulating Ising model nodes, reducing manufacturing costs from extensive wiring.

Segmented write assist cells boost bit line voltages to compensate for IR drops and improve write reliability in scaled memory.

A clock buffer control operation maintains phase matching between system and data clock signals.

Local word line drivers with intermediate voltage pauses reduce row hammer stress and data loss in memory arrays.

Segmented power saving modules raise source voltage in unselected banks to reduce leakage while maintaining layout area.

A semiconductor memory device uses a register to store verify values and a controller to generate reference voltages for programmable impedance elements.

An intermediate circuit detects memory card signals and generates conversion control signals to route data correctly.

Phase change synapses enable spike timing-dependent plasticity without complex control logic.

A memory pre-charging circuit dynamically disconnects power supply terminals during inactive row active states to conserve current.

A memory system uses a mapping controller to adjust error correction code generation based on detected defects.

Dual buffers store consecutive data lines while a data strobe driver clocks sequential byte output, reducing read latency in non-volatile memory devices.

Dual precharge circuits charge separate bitline sets concurrently with write operations to reduce cycle time.

A semiconductor internal voltage generator circuit adjusts voltage levels based on operation speed information to maintain stable power delivery.

A memory controller activates specific bank segments to limit current draw during data access operations.

Segmented twelve-transistor bit-cell resolves low voltage writability and read stability issues through independent port threshold tuning.

Selective powering of SRAM banks maintains access speed while reducing power consumption.

A domino read local evaluation circuit predicts write data to control bitline precharging in double pumped arrays.

A six-transistor shift register simplifies circuit structure to reduce noise interference and enhance reliability in liquid crystal display drivers.

An overdriver boosts an internal voltage supply terminal to prevent voltage droop during continuous high-speed write operations.

Single-bank memory multiplexing selects data from columns using shared circuitry to reduce dynamic power consumption.

Delayed wordline assertion synchronizes with write assist enable signals to activate memory cells after bitline voltage stabilization.

A two-phase sequential write scheme in an 8T SRAM cell achieves 100% writability and target Static Noise Margin without power-hungry assist circuits.

A detection circuit compares resistance values between a reference memory cell and a target cell within the same block to determine stored data.

Dynamic voltage boosting restores FeRAM read speeds at low temperatures while minimizing power consumption.

Segmentation diodes isolate adjacent memory cells to prevent disturb conditions while reducing leakage current.

A semiconductor memory page buffer uses a shifting pointer to route data directly to active columns.

A floating body memory cell uses a sense amplifier to equalize and pre-charge bit lines for direct data sensing.

Capacitor voltage comparison drives programming pulse width to resolve non-linear conductance variability during synaptic weight transfer.

Extending the Fine Granularity Refresh mode duration prevents premature exit that causes redundant refresh cycles, thereby reducing DRAM power consumption.

A DRAM pump system dynamically activates spare pump devices to supply sufficient current for higher refresh rates.

A CMOS under array memory structure places sense amplifiers beneath bit lines to optimize layout efficiency.

Buffer circuit delays adjacent shift register outputs, reducing voltage overlap from 11V to 1.5V and preventing sampling errors.

Adjusting the voltage sinking rate on selected bit lines resolves the trade-off between writing speed and state transition reliability in phase-change memory.

Address-based delay adjustment aligns strobe signals with line propagation time, reducing power consumption from unnecessary extended driving.

A semiconductor device routes test data through an input/output circuit using external clock signals to bypass the memory array.

A read reference circuit matches bit line and transmission gate parasitics to generate a dynamic current for fast storage class memory sensing.

Dynamic voltage adjustment reduces charge pump workload and saves power by matching input levels to memory device profiles.

Control circuitry measures delay mismatch between differential signal paths and transmits compensation values to adjust phase alignment.

A global read-write tracking circuit generates negative bit line firing timing signals to emulate voltage transitions across the memory array.

A reference bit line cancels gate leakage currents to improve read accuracy while reducing lithography complexity.

A subtractive top via process forms an integral bottom electrode contact for embedded memory structures.

Direct transfer between sense amplifiers bypasses I/O buffers and cache memories to reduce latency.

A hardware memory test unit checks data storage sections for transient faults before processor access.

Dynamic read-cell circuits using low-barrier nanomagnets enhance sensing margins without complex peripheral amplifiers.

A command scheduling component prioritizes necessary memory operations to enhance system performance.