Digital Storage TRIZ Cases

Parallel NFET and PFET branches route program and erase voltages in RRAM while keeping low-voltage devices within SOA to cut leakage.

Interleaved booster cells reconfigure PMOS and NMOS connections to speed word-line rise and limit parasitic effects in memory arrays.

Gap-bridged closed-loop magnetic conductors let domain walls cross spiral sections, expanding counting range without larger chip area or higher defect risk.

A boosting circuit detects core-voltage drops during mismatch compensation and supports sensing to preserve margin and prevent malfunctions.

A bismuth-metal SOT layer keeps a high spin Hall angle while withstanding 400°C BEOL annealing for stable MRAM switching.

By scanning only high-error word lines, the memory system detects read disturb risk and triggers refresh with less host blocking.

Multiple write drivers and overlapping column select paths enable multi-word row writes in fewer clock cycles, increasing memory write throughput.

Selective series resistors and parallel switches cut hold current in memory cell lines to prevent read-write failures and oscillation.

A dielectric interfacial layer in SOT MRAM boosts spin polarization, lowers programming current, and protects tunnel-layer reliability.

Selective power-amplifier shutdown keeps inactive non-rank0 DRAM logic non-floating, cutting leakage current and stack power waste.

Nano-pores in the MTJ free layer cut saturation magnetization without thinning or added elements, reducing write errors and magnetic interference.

CMOS transmission-gate selection boosts write current in resistive memory cells while lowering power use and improving cell uniformity.

Pre-verify logic applies inhibition voltage only to selected memory cells, limiting over-programming and narrowing threshold voltage distribution.

A dual-gate read transistor in a stacked 3D memory array cuts read word line IR drop, enabling longer lines, smaller cells, and higher capacity.

Pre-setting a negative well voltage lets the decoder switch underdrive onto the word line faster, improving memory word line setting.

An amorphous metal oxide, blocking, and buffer stack suppresses oxygen diffusion and crystal transfer to stabilize MTJ resistance and switching at high temperature.

Independent currents in three conductor layers generate spin orbit torque to write magnetoresistance states without direct element current.

Replica-cell tracking generates reference voltages to offset PVT variation in ReRAM crossbars, cutting read-bit errors in multi-bit reads.

Discontinuous stable interface layers and multi-component electrodes help scaled RRAM lower forming voltage and current while stabilizing filament growth.

Separate bias control for memory cells and peripheral circuits cuts leakage current and improves reliability across changing conditions.

Bank-specific CDC buffers let fast compute engines access slower SRAM banks with lower latency, better bandwidth use, and less power.

An antiferromagnetic storage layer with reversible Hall coefficient improves write speed and data stability while limiting crystallinity variation.

Holding portions store transistor currents so product-sum operations use less power and stay more stable against temperature and device variation.

Vertical memory cells use graded dopant regions near the channel to raise integration density without relying on costly fine patterning.

A pipelined CAM-based cumulative distribution table sampler cuts latency, energy, and area while suppressing timing and power side-channel leakage.

Symmetrical arrays and dual current comparison offset bit-line leakage, keeping memory read windows accurate across temperatures.

A vertical MOSFET with SiGe source/drain shrinks memory cell area while improving read/write behavior, contact resistance, and floating body control.

A hybrid sense amplifier layout shares amplifiers across banks while adding bank-specific paths to curb usage-based disturbance and command conflicts.

Separating bit lines and complementary bit lines into different tracks cuts 4Cpp SRAM metal congestion and avoids fin cuts and shared contacts.

Separate write-data wiring pairs by memory bank group to cut RC loading, reduce signal distortion, and speed writes.

Bit-line precharge and column multiplexing improve pseudo dual-port SRAM speed and signal stability without enlarging memory cells.

Separate clock-tree alignment and per-device tuning reduce skew on command/address buses, improving memory read/write accuracy.

Multiple-phase data clocks and delayed test-pattern training tune duty cycle settings to maintain read margins across voltage, temperature, and high-frequency shifts.

Voltage-aware read and write assist control lets SRAM macros adapt across DVFS ranges, reducing power loss and data destruction risk.

Separating array power-up from bit line pre-charge with a secondary sleep loop reduces memory wake-up peak current by up to 42%.

Multiple ferroelectric capacitors store duplicate data in each cell, cutting write-back after destructive reads to improve density, latency, and endurance.

An HfO2 interfacial layer boosts remnant polarization in thin hafnium-based ferroelectric films while reducing leakage current for scaled memory devices.

Swap commands and addresses let a memory chip set swap mode without a separate pin, reducing PCB wiring interference and preserving signal integrity.

Multiple enable pulses on one wordline let pseudo multi-port memory raise read throughput while avoiding four-port SRAM cost and area.

Hybrid offset compensation tunes N-type and P-type sense amplifiers to improve DRAM sensing accuracy under PVT variation.

An inverted T-shaped bottom electrode concentrates the electric field at its tip, accelerating filament formation and RRAM programming.

Preallocated redundancy units and nonvolatile mapping let volatile memory replace failed units faster while preserving remap data after power loss.

A two-phase fluid loop uses assisted condensation to control semiconductor temperature and pressure while reducing thermal stress during testing.

Multi-step column select signals compensate line resistance and capacitance, improving access to distant memory cells.

Selective bit line clamping cuts DC current in unselected TDP memory columns, improving electromigration compliance and read-mode power use.

Paired selector-only memory cells written with opposite polarities enable differential reads that offset Vth drift and preserve data integrity over time.

Photon avalanche carrier trapping in a PN-junction waveguide enables non-volatile optical storage on PICs while reducing OEO conversions.

Integrating MRAM with a magnetic-core inductor on one chip cuts off-chip assembly, reducing thickness and manufacturing cost.

Initialization-stage training uses oscillator codes to correct clock-data timing drift from voltage and temperature changes with less startup overhead.

Shared word line pads and vertically stacked memory cells cut pad-region area and raise semiconductor memory integration density.