Bit Line Clamp Control for Low-Power TDP Memory Reads
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Solution Overview
Problem
Memory circuits in advanced technology nodes face reliability issues such as electromigration violations and increased power consumption due to continuous DC paths in unselected columns during read operations, particularly in True Dual Port (TDP) memory circuits.
Innovation Solution
Implementing clamp circuits that selectively enable and disable bit lines based on operational modes, such as read first, write first, and no change modes, to prevent DC current paths in unselected columns, thereby reducing power consumption and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clamp circuits are continuously enabled in all columns during read operations, then bit line voltage transitions are limited for sensing circuit detection, but DC current paths form in unselected columns causing electromigration violations and increased power consumption
Solution Approach 1:
The clamp circuits are implemented with dynamic control that enables or disables clamping based on whether the column is selected for the current read operation. This dynamic behavior allows the system to adapt to different operational states, enabling clamping only when necessary for selected columns while leaving unselected columns in a high-impedance state to avoid DC current paths.
Solution Approach 2:
The patent applies different clamp circuit configurations to different columns based on their selection status. Selected columns have clamp circuits enabled with appropriate clamp values to limit voltage transitions, while unselected columns have clamp circuits disabled or configured with high impedance to prevent DC current flow. This local differentiation resolves the contradiction by applying clamping only where needed.
2Loss of energy
If clamp circuits are disabled in unselected columns, then power consumption and electromigration issues are reduced, but bit line voltage control during read operations is compromised
Solution Approach 1:
The memory array is segmented into selected and unselected columns, with clamp circuits independently controlled for each segment. This segmentation allows the system to apply different clamp configurations to different segments based on their operational requirements, enabling power savings in unselected columns while maintaining data integrity in selected columns.
Solution Approach 2:
The clamp circuit parameters (enable/disable control, clamp voltage levels) are dynamically changed based on column selection status and read operation requirements. This parameter adjustment allows the system to optimize power consumption by disabling clamping in unselected columns while maintaining appropriate clamping in selected columns to ensure reliable data sensing.
3Stability of the object's composition
If clamp circuits are enabled during write first and no change modes, then bit line voltage transitions are controlled, but unnecessary DC current paths are created increasing power consumption
Solution Approach 1:
The clamp circuits are controlled to be periodically enabled or disabled based on the operational mode and column selection, rather than remaining continuously enabled. This periodic control ensures clamping is active only when necessary for voltage stability during actual read operations, while being disabled during write first and no change modes to eliminate unnecessary power consumption.
Data Source
AI summary
A memory circuit is disclosed. The memory circuit includes a plurality of bit lines; a plurality of memory cells arranged in columns, each memory cell connected to a pair of bit lines; and a plurality of clamp circuits, each including a first clamp and logic circuit connected to a first bit line and a second clamp and logic circuit connected to a second bit line, where the first clamp and logic circuit is configured to selectively clamp the first bit line in response to the memory circuit operating in a particular mode, and where the second clamp and logic circuit is configured to selectively clamp the second bit line in response to the memory circuit operating in the particular mode.