Memory Device Read Latency Reduction via Buffering
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Solution Overview
Problem
Non-volatile memory devices, such as flash memory, face limitations in power consumption and operational speed, leading to high latency issues that can impact microprocessor performance due to slow access times and inefficient communication protocols.
Innovation Solution
Implementing a memory device architecture with a memory array and buffers that utilize data strobe timing and interleaved data line access to reduce read latency, allowing for concurrent access and output of data lines, and employing output circuitry to manage data transfer efficiently across multiple memory array accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash memory architecture is used, then non-volatile storage is achieved, but read latency is high and access speed is slow
Solution Approach 1:
The patent implements a buffer that pre-fetches and stores data from the memory array before it is requested by the host. The buffer is filled in advance during idle periods or in parallel with other operations, so when a read request arrives, the data is already available or nearly available, significantly reducing the read latency and improving access speed without requiring architectural changes to the memory array itself.
2Productivity
If traditional memory access protocols are used, then communication between host and memory is maintained, but additional latency is introduced by protocol overhead
Solution Approach 1:
The buffer performs preliminary data preparation and staging before host requests are fully processed. By having data ready in the buffer in advance, the system可以减少 the time spent on data retrieval and protocol handshaking, thereby improving overall data transfer efficiency and reducing protocol-related latency.
3Speed
If microprocessor operates at high speed, then processing performance is improved, but memory latency becomes a bottleneck
Solution Approach 1:
The buffer acts as a staging area that prepares data in advance, decoupling the high-speed microprocessor from the slower memory array. While the processor operates at high speed, the buffer ensures data is ready or nearly ready, minimizing wait states and memory access time, thus eliminating the bottleneck effect.
4Device complexity
If multiple data lines are accessed sequentially, then memory array structure is simple, but read latency increases
Solution Approach 1:
The patent divides the data transfer function into two segments: the memory array remains structurally simple with sequential access capability, while the buffer handles parallel data preparation and staging. This segmentation allows the memory array to maintain its simple structure while the buffer performs concurrent data line access and preparation, reducing overall read latency without complicating the core memory array architecture.
Data Source
AI summary
A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.