SRAM Write Assist Cells for Voltage Margin
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Solution Overview
Problem
Current SRAM memory devices face limitations in configuration and operation, particularly with shrinking memory cell sizes leading to reduced read and write voltage margins due to increased IR drops in bit lines, which can result in unreliable data access and reduced performance.
Innovation Solution
The integration of Write Assist (WAS) cells directly within the SRAM array, rather than in input/output circuits, to maintain and amplify bit line voltages, thereby enhancing read and write margins and ensuring reliable operations without the need for additional circuitry or increased periphery costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM memory cell size is reduced to increase memory density, then memory capacity increases, but read and write voltage margins are reduced due to increased IR drops in bit lines
Solution Approach 1:
The bit line is divided into multiple segments with separate write assist cells for each segment. This segmentation allows localized voltage boosting at different positions along the bit line, effectively compensating for IR drops that increase with longer bit lines in high-density memory arrays.
Solution Approach 2:
Write assist cells are introduced as intermediary components between the word line and bit line. These assist cells actively boost the bit line voltage during write operations, mediating the voltage drop issue and enabling reliable writes even in deeply scaled memory cells with reduced voltage margins.
2Reliability
If Write Assist cells are integrated directly within the SRAM array, then bit line voltage is maintained and write reliability is improved, but device complexity increases
Solution Approach 1:
The write assist cell is merged with the standard SRAM cell structure, sharing common transistors and circuit elements. This integration combines the storage function and voltage boosting function into a unified cell design, improving write reliability without proportionally increasing device complexity.
Solution Approach 2:
The write assist cell performs multiple functions: it acts as a voltage booster during write operations, functions as a storage element, and can operate as a standard SRAM cell when the assist function is not needed. This multi-functionality reduces the need for separate dedicated assist circuits, thereby limiting the increase in overall device complexity.
3Device complexity
If Write Assist cells are placed in input/output circuits rather than within the SRAM array, then device complexity is reduced, but bit line voltage cannot be maintained and write reliability deteriorates
Solution Approach 1:
Write assist cells are positioned locally within the SRAM array at specific locations where bit line voltage boosting is most needed. This local placement ensures that voltage margins are maintained at the point of data writing, improving write reliability without requiring global circuit modifications that would increase overall device complexity.
Data Source
AI summary
A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.