Memory System ECC Mapping Controller
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Solution Overview
Problem
As memory device capacity increases, it becomes increasingly difficult to fabricate devices completely free of defective memory cells, necessitating methods to correct errors and utilize redundant cells or error correction codes (ECC) to manage defects.
Innovation Solution
A memory system incorporating an error correction code generation circuit, data mapping circuits, and a memory module that generates and applies error correction codes to write data, maps symbols to datawords, and stores these in memory chips, with a mapping controller to adjust mapping methods based on error detection history to optimize error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The memory device is divided into multiple banks, with each bank containing independent data memory cells and ECC memory cells. This segmentation allows errors to be isolated and corrected within specific banks rather than affecting the entire memory device, enabling higher overall capacity while maintaining reliability through localized error management.
Solution Approach 2:
ECC memory cells are pre-configured and positioned alongside data memory cells during fabrication. Error correction codes are generated and stored in advance during write operations, enabling errors to be corrected before they propagate during read operations. This preliminary preparation of correction mechanisms allows the system to handle defects that inevitably arise in high-capacity devices.
2Reliability
If error correction codes are generated and stored for all write data, then error correction capability is improved, but memory bandwidth and storage efficiency deteriorate
Solution Approach 1:
Different ECC schemes are applied to different banks based on their specific error characteristics. Some banks use stronger error correction with more ECC bits, while others use lighter schemes. This localized differentiation optimizes the balance between error correction capability and bandwidth utilization, avoiding the need to apply uniform heavy ECC to all data.
Solution Approach 2:
The system generates and stores ECC for only a portion of the total memory capacity at any given time, rather than requiring full ECC coverage for all data simultaneously. This partial application of error correction allows the memory system to achieve adequate error protection while maintaining higher effective bandwidth for active data operations.
Data Source
AI summary
A memory system includes: an error correction code generation circuit suitable for generating an error correction code including one or more symbols for write data including a plurality of symbols, to output a codeword including the write data and the error correction code; a first data mapping circuit suitable for mapping the symbols of the codeword to a dataword; and a memory suitable for storing the dataword.