Semiconductor Memory Page Buffer Pointer Logic
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Solution Overview
Problem
Conventional NAND flash memory devices experience degraded data write speed due to the redundancy technique used to replace defective columns, which increases chip size and requires extensive data movement between normal and redundancy columns.
Innovation Solution
A semiconductor memory device configuration that includes latch circuits to identify defective columns and shift a pointer around them, allowing data to be written directly to normal columns without transferring through redundancy columns, thereby reducing interconnection length and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy technique is used to replace defective columns, then data integrity is improved, but data write speed is degraded
Solution Approach 1:
The patent divides the page buffer into multiple buffer regions, each associated with specific columns. By segmenting the buffer management, the system can directly write data to the appropriate buffer region without requiring movement between normal and redundancy columns, thus maintaining data integrity while improving write speed.
Solution Approach 2:
The patent introduces a buffer region as an intermediary structure between the data input unit and the memory cell array. This buffer region directly receives and holds data for both normal and defective columns, eliminating the need for data movement between different column types and resolving the speed-integrity contradiction.
2Reliability
If redundancy technique is used to replace defective columns, then data integrity is improved, but chip size is increased
Solution Approach 1:
The patent makes the buffer regions multi-functional by enabling them to store data for both normal columns and defective columns. This universal buffer structure eliminates the need for separate redundancy column structures, maintaining data integrity while reducing overall chip size.
Solution Approach 2:
The patent merges the functionality of normal column buffers and redundancy column buffers into a unified buffer structure. By combining these previously separate elements, the system maintains the ability to handle defective columns while reducing the total chip area required.
3Reliability
If redundancy technique is used to replace defective columns, then data integrity is improved, but data movement requirements are increased
Solution Approach 1:
The patent extracts the data movement requirement from the system by enabling direct writing to buffer regions associated with defective columns. The buffer region acts as a direct destination for data, eliminating the intermediate movement step through redundancy columns and simplifying the data path.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, and first to third latch circuits. The first latch circuits hold information as to whether an associated column is defective. A pointer is set in the second latch circuits. The third latch circuits hold write data or read data. One of the third latch circuits is activated at a time the pointer is set to an associated second latch circuit when an associated first latch circuit holds the information indicating that the associated column is not defective. The pointer is sequentially shifted among the second latch circuits in synchronization with a clock. In shifting the pointer, the pointer skips one of the second latch circuits associated with one of the first latch circuit which holds the information indicating that the associated column is defective.