SRAM Multiplexing Apparatus for Power and Speed Optimization
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Solution Overview
Problem
Modern SRAM memory circuits face delays in read operations due to high capacitance on bit lines resulting from a large number of memory cells, which can be mitigated by partitioning bit lines into local and global lines, but further improvements are needed to reduce power consumption and enhance access time.
Innovation Solution
A two-level multiplexing apparatus is introduced, comprising local and global input/output multiplexers and sense amplifiers, which selectively activate bit lines to reduce capacitance and power consumption by ensuring only one global bit line transitions during a read operation, thereby optimizing data transfer through a network of memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines are partitioned into local and global lines, then access time is reduced due to lower capacitance, but device complexity increases due to additional multiplexing structures
Solution Approach 1:
The patent divides the bit line into two distinct segments: local bit lines connected to memory cells and global bit lines connected to sense amplifiers. This segmentation reduces the capacitance on each segment, enabling faster switching and reduced access time while managing complexity through functional separation.
Solution Approach 2:
The patent introduces local I/O multiplexers as intermediary components between the local bit lines and global bit lines. These multiplexers act as mediators that selectively connect local bit lines to global bit lines, enabling fast local operations while maintaining controlled global signal transitions.
2Quantity of substance
If the number of memory cells coupled to bit lines is increased, then memory capacity is improved, but power consumption increases due to higher capacitance
Solution Approach 1:
The patent segments the bit line into local and global portions, allowing memory capacity to be increased by adding more local bit lines without proportionally increasing the capacitance of global bit lines. Power consumption is reduced because only selected global bit lines transition during read operations.
Solution Approach 2:
The patent implements partial action by ensuring that only one global bit line transitions during a read operation, rather than all global bit lines transitioning simultaneously. This reduces the total energy consumption while still supporting increased memory capacity through multiple local bit lines.
3Adaptability or versatility
If global bit lines are allowed to transition freely, then data transfer flexibility is improved, but power consumption increases due to multiple simultaneous transitions
Solution Approach 1:
The patent implements dynamic control through local I/O multiplexers that selectively connect local bit lines to global bit lines based on read operation requirements. This dynamic switching ensures that only the necessary global bit line transitions during each operation, maintaining flexibility while reducing power consumption.
Solution Approach 2:
The patent employs sense amplifiers that detect the state of local bit lines and provide feedback control signals to the local I/O multiplexers. This feedback mechanism ensures that global bit lines are transitioned only when and where data transfer is actually needed, optimizing both flexibility and power efficiency.
Data Source
AI summary
An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.