Selectively-Powered SRAM Banks for Cache Power-Speed Trade-offs
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Solution Overview
Problem
As CPU cache sizes increase, access speeds suffer, and existing methods for conserving power in mobile devices, such as placing devices in standby mode, are inefficient in managing the power states of static random access memory (SRAM) cells, leading to suboptimal power usage and performance.
Innovation Solution
A selectively-powered memory device that includes power circuitry to concurrently power a subset of SRAM cells at a normal-operation voltage while others are at a power-saving voltage, allowing for granular control over memory cell power states, enabling efficient access and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM cache size is increased to improve processing power, then memory capacity increases, but access speed deteriorates
Solution Approach 1:
The patent divides the SRAM cache into multiple banks, where each bank can be independently accessed and powered. This segmentation allows the system to maintain large total capacity while enabling fast access to individual banks, resolving the contradiction between increased memory capacity and maintained access speed.
2Loss of energy
If device is placed in standby mode to conserve power, then power consumption decreases, but memory access performance deteriorates
Solution Approach 1:
The patent implements dynamic power management where SRAM banks can be selectively powered up or down based on access requirements. During standby mode, inactive banks are powered down to conserve energy, while during active operations, only the necessary banks are powered up, maintaining performance while reducing overall power consumption.
Solution Approach 2:
The patent applies different power states to different SRAM banks based on their usage status. Instead of uniformly powering the entire cache, individual banks receive appropriate power levels locally, allowing the system to optimize the balance between power consumption and performance on a per-bank basis.
3Loss of energy
If entire SRAM cache is powered down to save power, then power consumption decreases, but data retention capability deteriorates
Solution Approach 1:
By segmenting the cache into independently controllable banks, the system can maintain data in powered-up banks while powering down unused banks. This ensures data retention reliability for active data without requiring the entire cache to remain powered, thus reducing power consumption.
Data Source
AI summary
Embodiments provide methods, apparatuses and systems including a plurality of memory cells configured to store bit values while being powered at a power-saving voltage lower than a normal-operation voltage during operation of a host apparatus, and power circuitry coupled to the plurality of memory cells. The power circuitry is configured to selectively power a first subset of the plurality of memory cells at the normal-operation voltage during operation of the host apparatus while concurrently powering a second subset of the plurality of memory cells at the power-saving voltage. The first and second subsets being different subsets of the memory cells.