Memory Device Wordline Assertion Timing for Write Assist
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Solution Overview
Problem
In modem memory devices, the effectiveness of write assist mechanisms, such as capacitive based negative bitline boost, is compromised when the peripheral voltage supply is reduced relative to the cell voltage supply, leading to reduced writeability of memory cells.
Innovation Solution
Implementing a delayed wordline assertion technique, where the wordline signal is asserted only after the write assist enable signal, ensuring the wordline is activated after the bitline voltage has reached the desired level, thereby maximizing the boost effect and preventing parasitic read effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the peripheral voltage supply is reduced to save power, then power consumption is reduced, but the write assist mechanism effectiveness is reduced
Solution Approach 1:
The wordline assertion is delayed until after the write assist mechanism has been activated and the bitline voltage has reached the desired level. This preliminary sequencing ensures that the write assist boost is fully established before the wordline is asserted, preventing parasitic read effects and maximizing the writeability improvement even when operating from reduced peripheral voltage supply.
2Productivity
If the wordline is asserted early to improve write performance, then write speed is improved, but parasitic read effects occur and write assist effectiveness is reduced
Solution Approach 1:
The write assist mechanism is activated before the wordline is asserted. By sequencing the wordline assertion to occur after the write assist enable signal, the patent ensures that the bitline voltage has reached the desired level before the wordline is asserted, thereby preventing parasitic read effects while maintaining fast write operation.
Solution Approach 2:
The control circuitry monitors the write assist enable signal timing and uses this feedback to control the wordline assertion timing. This feedback mechanism ensures that the wordline is asserted only after the write assist mechanism has been activated, preventing parasitic read effects while maintaining write performance.
3Use of energy by moving object
If the peripheral voltage supply is reduced below cell voltage supply, then power savings are achieved, but writeability of memory cells is reduced
Solution Approach 1:
The wordline assertion is delayed until after the write assist mechanism has been activated. This sequencing ensures that the write assist boost is fully established before the wordline is asserted, maintaining writeability even when the peripheral voltage supply is reduced below the cell voltage supply level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances writeability without adversely affecting write performance, as the write operation can be completed quickly with improved voltage differential between bitlines, reducing dynamic energy and stability failures.
Implementation Method 1
One particular approach is the negative bitline boost (NBLB) approach, which is typically a capacitive based approach
Data Source
AI summary
The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.