Memory Array Segmentation Using Diode Select Devices
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Solution Overview
Problem
As flash memory devices increase in density, they face issues with disturb conditions due to interaction between adjacent memory cells, and the use of segmentation transistors to divide arrays into smaller sections is inefficient as they are larger than the memory cells and do not scale with cell size, leading to reduced array efficiency.
Innovation Solution
The implementation of a memory array architecture that uses smaller segmentation elements, such as diodes, which are identical to the select devices for variable resistance memory cells, to segment bit and word lines, allowing for efficient scaling and reduced die space usage, along with biasing lines to forward or reverse bias local bit lines for selecting specific cells, thereby improving memory cell accessibility and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If segmentation transistors are used to divide memory arrays into smaller sections, then memory cell accessibility is improved, but device area efficiency deteriorates because segmentation transistors are larger than memory cells and do not scale with cell size
Solution Approach 1:
The patent changes the type of segmentation element from transistor to diode, which has different electrical characteristics and physical dimensions. Diodes can be fabricated with smaller footprints that scale with memory cell dimensions, thereby improving die space efficiency while maintaining the segmentation function for memory cell accessibility.
Solution Approach 2:
The segmentation diodes are formed using the same fabrication process and structural characteristics as the memory cell select devices. This copying approach ensures that segmentation elements scale proportionally with memory cell size, allowing both to shrink together as technology nodes decrease, thus maintaining area efficiency.
2Quantity of substance
If memory cell size is reduced to increase density, then memory density is improved, but disturb conditions worsen due to increased interaction between adjacent memory cells
Solution Approach 1:
The patent divides the memory array into smaller segments using diode segmentation elements. This segmentation isolates adjacent memory cells into separate regions, reducing unwanted electrical interaction and disturb conditions between cells while allowing higher density within each segment. The segmentation creates electrical boundaries that prevent cross-talk.
Solution Approach 2:
The diode segmentation elements act as intermediary components between adjacent memory cell segments. These diodes control and regulate electrical flow between segments, preventing direct interaction that causes disturb conditions while maintaining the ability to access individual cells. The intermediary diodes isolate segments electrically.
3Device complexity
If traditional segmentation transistors are used, then memory array segmentation is achieved, but manufacturing complexity increases due to difficulty in fabricating and tightly packing small transistors
Solution Approach 1:
The patent uses diodes that serve dual functions: as segmentation elements to divide the memory array and as select devices within the memory cells themselves. This multi-functionality eliminates the need for separate segmentation transistor structures, simplifying fabrication processes and reducing manufacturing complexity while achieving both segmentation and cell selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient scaling of segmentation elements with memory cells, reducing die area usage and improving memory array efficiency by enabling precise control over memory cell selection and operation, thus enhancing memory density and performance.
Implementation Method 1
The segmentation elements are diodes... biasing lines to forward or reverse bias local bit lines for selecting specific cells
Data Source
AI summary
Memories may include a first bi-directional select device connected between a first access line and a second access line, and a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells comprises a respective second bi-directional select device, of a plurality of second bi-directional select devices, and a respective programmable element, of a plurality of programmable elements, connected in series.