Clock Signal Processing Circuit Phase Matching
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Solution Overview
Problem
Conventional semiconductor memory apparatuses require repeated clock training operations during initial power-up and self-refresh cycles, leading to increased time delays and inefficiencies due to the need for phase matching of system and data clock signals.
Innovation Solution
Implementing a clock signal processing circuit that performs clock training only once during the initial power-up and uses a clock buffer control operation to maintain phase matching, preventing phase errors by fixing output signals to determined levels until the data clock signal toggles, and allowing the semiconductor apparatus to directly enter normal operation without waiting for additional clock training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock training operation is performed repeatedly during initial power-up and self-refresh cycles, then phase matching between system clock signal and data clock signal is maintained, but time delay and operational inefficiency increase
Solution Approach 1:
The patent applies preliminary action by performing clock training operation only once during initial power-up to establish phase matching between system clock signal and data clock signal. The training circuit is configured to refrain from performing clock training operation during subsequent self-refresh cycles, relying instead on the pre-established phase relationship to maintain reliability without repeated time-consuming training operations.
2Reliability
If clock training operation is performed during self-refresh exit and clock training entry commands, then phase matching is ensured, but operational efficiency decreases due to repeated training
Solution Approach 1:
The patent applies self-service by configuring the training circuit to maintain phase matching through the clock buffer control operation without requiring repeated clock training operations during self-refresh cycles. The system uses the established phase relationship from initial power-up to automatically maintain synchronization during subsequent operations, eliminating the need for self-service training operations during self-refresh exit and clock training entry commands.
3Reliability
If clock buffer output is fixed to determined levels until data clock signal toggles, then phase errors are prevented, but flexibility in clock signal adjustment is reduced
Solution Approach 1:
The patent applies dynamics by implementing a clock buffer control operation that dynamically adjusts the clock buffer output based on the state of the data clock signal. The control signal generated by the control circuit enables the clock buffer to fix its output to determined levels when needed for phase error prevention, while allowing flexibility in clock signal adjustment when the data clock signal transitions, thus balancing reliability and adaptability.
Data Source
AI summary
A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.