Floating Body Memory Cell Circuit Simplification
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Solution Overview
Problem
Conventional semiconductor memory devices with floating body memory cells have complex circuit configurations and require a refresh operation after data read, complicating operation and control, and are not efficient in reducing layout size.
Innovation Solution
A semiconductor memory device with a memory cell array comprising first and second blocks, each with a floating body, connected to bit lines and word lines, utilizing a sense amplifier for equalizing and pre-charging bit lines, and bit line isolation gates for data transmission and isolation, eliminating the need for reference memory cells and simplifying the read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional capacitor-based dynamic memory cells are used, then data storage is achieved, but the layout size cannot be significantly reduced
Solution Approach 1:
The patent extracts and eliminates the capacitor component from the memory cell structure, using only a single transistor with a floating body to perform memory functions. This removal of the capacitor simplifies the circuit configuration while maintaining data storage capability through majority carrier storage in the floating body region.
Solution Approach 2:
The floating body transistor serves multiple functions: it acts as both the storage element (replacing the capacitor) and the access transistor simultaneously. The floating body region stores majority carriers to represent data, while the transistor structure provides read and write access, eliminating the need for separate capacitor and transistor components.
2Area of stationary object
If floating body transistors are used to reduce layout size, then area is reduced, but the circuit configuration becomes complex requiring reference memory cells and multiple sense amplifiers
Solution Approach 1:
The patent merges the memory cell array with the sense amplifier circuitry by directly connecting bit lines to sense amplifiers without requiring separate reference memory cells. The sense amplifiers are configured to directly sense voltage differences on bit lines caused by floating body charge, eliminating the need for additional reference cell structures and complex decoding circuits.
Solution Approach 2:
Instead of using conventional sense amplifiers that require reference cells for comparison, the patent inverts the approach by using the floating body charge itself to directly create voltage differences on bit lines that can be sensed. The read operation senses the voltage drop caused by hole discharge from the floating body, rather than comparing against a reference cell.
3Area of stationary object
If floating body memory cells are used, then layout size is reduced, but refresh operations are required after data read
Solution Approach 1:
The patent implements a continuous refresh mechanism where the refresh operation is seamlessly integrated with the normal read/write operations. The floating body is periodically recharged through impact ionization during normal operation, ensuring continuous data retention without requiring separate refresh cycles. This maintains the useful action of data storage continuously without interruption.
Solution Approach 2:
The floating body transistor performs self-refresh through impact ionization during normal read and write operations. When voltage is applied to the drain during operations, electron-hole pairs are generated and holes are automatically injected into the floating body to replenish stored charge, enabling the memory cell to refresh itself without external control signals.
4Area of stationary object
If conventional memory cells with capacitors are used, then operation is straightforward, but layout size cannot be significantly reduced
Solution Approach 1:
The patent changes the fundamental parameter for data storage from electric charge in a capacitor to majority carrier concentration in a floating body region. This parameter change enables new mechanisms for data retention through impact ionization and hole injection, providing reliable data storage while enabling significant area reduction through the single-transistor structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the circuit configuration, reduces the need for refresh operations, and allows for smaller layout sizes by directly using floating body transistors as memory cells, enhancing data read and write operations without the complexity of reference cells.
Implementation Method 1
A floating body transistor stores a majority carrier
Implementation Method 2
electron-hole pairs are produced around a drain of the NMOS transistors, which form the memory cells due to impact ionization
Implementation Method 3
a sense amplifier for equalizing and pre-charging bit lines
Data Source
AI summary
A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.