Semiconductor Device Test Data Bypass via I/O Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices require dedicated circuits for test data bypass, leading to increased complexity and size, which hinders miniaturization efforts.
Innovation Solution
A semiconductor device configuration that includes a memory circuit with a matrix of memory cells, input/output circuits for data transfer, and a control circuit generating signals to control these circuits, allowing test data to bypass the memory array and directly output to logic circuits using external clock signals, eliminating the need for dedicated bypass circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated write data bypass circuit or scan bypass enable logic circuit is provided for bypassing memory array, then test data can be transferred to logic circuit, but device complexity increases and miniaturization is hindered
Solution Approach 1:
The input/output circuit is designed to perform multiple functions: it serves as both a data transfer path during normal operation and as a bypass path during test operations. By controlling the selection circuit with a test mode signal, the same physical circuit infrastructure is reused for both normal data access and test data bypass, eliminating the need for separate dedicated bypass circuits and thereby reducing device complexity while maintaining test capability.
Solution Approach 2:
The patent merges the test bypass function with the existing input/output circuit infrastructure. Instead of providing separate dedicated bypass circuits, the test data bypass path is integrated into the existing data transfer path by using the same physical circuits (selection circuit, bit line, etc.) that are already present for normal operation, thereby reducing overall device complexity.
2Ease of operation
If dedicated bypass circuits are provided for test operations, then test data can be output to logic circuit, but area of semiconductor device increases
Solution Approach 1:
The input/output circuit is designed to perform multiple functions: it serves as both a data transfer path during normal operation and as a bypass path during test operations. By controlling the selection circuit with a test mode signal, the same physical circuit infrastructure is reused for both normal data access and test data bypass, eliminating the need for separate dedicated bypass circuits and thereby reducing device complexity while maintaining test capability.
Solution Approach 2:
The patent merges the test bypass function with the existing input/output circuit infrastructure. Instead of providing separate dedicated bypass circuits, the test data bypass path is integrated into the existing data transfer path by using the same physical circuits (selection circuit, bit line, etc.) that are already present for normal operation, thereby reducing overall device complexity.
Data Source
AI summary
A semiconductor device has a memory circuit and a logic circuit coupled with a memory circuit. the memory circuit included a memory array in which memory cells are arranged in a matrix, an input/output circuit for writing data to the memory cells and reading data from the memory cells, and a control circuit for generating a control signal for controlling the input/output circuit. In a test operation for testing the logic circuit, the input/output circuit receives a test data. The control circuit raises and lowers the control signal based on a rising and a falling of an external clock signal, thereby the test data is output to the logic circuit via the input/output circuit.