Non-Rank0 Memory Die Power Gating for Leakage Reduction
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Solution Overview
Problem
In 3D stackable DRAM configurations, non-rank0 memory dies consume unnecessary power due to leakage currents from inactive logic circuits, leading to significant power waste, especially in memory stacks with multiple dies.
Innovation Solution
Implementing power management techniques that selectively deactivate power amplifiers in non-rank0 memory dies, maintaining logic circuits in a non-floating state to reduce leakage currents and conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-rank0 memory dies are included in 3D stackable configurations, then memory capacity and integration density are improved, but power consumption increases due to leakage currents from inactive logic circuits
Solution Approach 1:
The patent applies local quality by differentiating the operational state of logic circuits based on their location and function within the memory stack. Rank0 dies maintain fully active logic circuits for controller communication, while non-rank0 dies deactivate unnecessary logic circuits that do not participate in data operations, thereby reducing leakage currents locally in inactive regions while preserving memory capacity.
Solution Approach 2:
The patent changes the operational parameter of logic circuits from active to deactivated state in non-rank0 memory dies. By controlling the power state of logic circuits based on their functional necessity, the system reduces leakage currents and power consumption while maintaining the physical presence and memory storage capability of all dies in the stack.
2Reliability
If all memory dies maintain active logic circuits, then data access speed and operational reliability are improved, but power waste increases due to unnecessary leakage currents
Solution Approach 1:
The patent implements local quality by selectively maintaining active logic circuits only where necessary for operational reliability (rank0 dies that communicate with the controller) while deactivating redundant logic circuits in non-rank0 dies. This localized differentiation preserves system reliability through proper controller interfacing while eliminating unnecessary power waste from inactive logic circuits.
Solution Approach 2:
The patent extracts and removes the unnecessary function of logic circuits from non-rank0 memory dies. By taking out the deactivated logic circuits from the operational system while retaining the memory array functionality, the patent eliminates power waste associated with these redundant components while maintaining data access reliability through the rank0 dies.
3Quantity of substance
If multiple memory dies are stacked in 3D configuration, then integration density is improved, but heat generation and power management complexity increase
Solution Approach 1:
The patent applies local quality by creating distinct power management zones within the 3D stacked configuration. Rank0 dies maintain full power and active logic circuits for controller communication, while non-rank0 dies operate in a reduced power state with deactivated logic circuits. This localized power management approach simplifies overall system complexity by providing clear differentiation between functional zones.
Solution Approach 2:
The patent implements dynamic power management where the operational state of logic circuits changes based on the die's position and function in the stack. The system dynamically adjusts power consumption by activating or deactivating logic circuits in response to operational requirements, thereby managing power complexity adaptively while maintaining high integration density through the 3D stack configuration.
Data Source
AI summary
A memory die configurable into a first die configuration or a second die configuration, includes a logic circuit; a power amplifier configured to regulate, for the logic circuit, an external supply voltage to an internal supply voltage having a target voltage level; a shorting circuit configured to receive a control signal and enable or disable the power amplifier based on the control signal; and a control circuit configured to generate the control signal based on whether the memory die is configured in the first die configuration or the second die configuration, as indicated by a configuration mode signal. The control circuit may generate the control signal with an enabled signal level such that the power amplifier is enabled by the shorting circuit. The control circuit may generate the control signal with a disabled signal level such that the power amplifier is disabled by the shorting circuit.