Pseudo Multi-Port Memory Using Multi-Pulse Wordlines for Read Throughput
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Solution Overview
Problem
Existing image processing blocks face a challenge in achieving increased pixel output bandwidth without incurring significant hardware cost and chip area penalties.
Innovation Solution
A pseudo multi-port memory design with two-port memory cell architecture and multiple enable pulses on a same wordline, utilizing a hierarchical bitline structure and a double pump scheme to enhance read throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-port SRAM bit-cells are used for cache storage, then hardware cost and chip area are controlled, but pixel output bandwidth and read throughput are limited
Solution Approach 1:
The patent applies multi-functionality by enabling a single memory cell to serve multiple read ports through time-multiplexed access. The memory cell architecture supports multiple read operations within one clock cycle by using different wordline enable pulses, allowing one physical memory structure to function as multiple logical memory ports, thereby increasing read throughput without proportionally increasing hardware cost
Solution Approach 2:
The patent employs periodic action through multiple enable pulses applied to the same wordline within a single clock cycle. These periodic enable pulses allow the memory cell to be accessed multiple times for read operations, effectively creating multiple read ports from a single physical memory structure. This time-division multiplexing approach increases throughput without requiring multiple separate memory banks
2Productivity
If multiple enable pulses are applied to the same wordline within one clock cycle, then read throughput is enhanced, but timing control complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitlines before the read operations commence. The bitline pre-charge circuit prepares the bitlines in advance by setting them to a known voltage state before the enable pulses are applied. This preliminary preparation ensures that when multiple read operations occur within one clock cycle, the bitlines are ready for each access without requiring complex re-initialization timing control
Solution Approach 2:
The patent uses an intermediary approach through the memory cell's inherent latch structure and bitline pre-charge mechanism. These intermediary elements buffer and manage the timing of multiple read operations, absorbing the complexity of coordinating multiple enable pulses. The pre-charge circuit acts as an intermediary that automatically prepares the read path before each enable pulse, simplifying the overall timing control logic
3Productivity
If two-port memory cell architecture is used instead of single-port, then read operations can be performed simultaneously, but write operation capability may be compromised
Solution Approach 1:
The patent applies dynamics by making the memory cell's port configuration flexible and time-variable. The same memory cell can dynamically switch between functioning as a read port or write port depending on which enable pulse is active at any given time within the clock cycle. This dynamic reconfiguration allows the memory cell to support both multiple concurrent reads and write operations, adapting its functionality based on the operational phase
Data Source
AI summary
A pseudo multi-port memory includes a memory array, a row decoder circuit, a timing controller circuit, a sense amplifier circuit, and a write driver circuit. The timing controller circuit outputs a timing control signal to the row decoder circuit, wherein during one memory clock cycle, the row decoder circuit is controlled by the timing control signal to make a read wordline (RWL) signal have an enable pulse and a write wordline (WWL) signal have multiple enable pulses. During one memory clock cycle, the sense amplifier circuit performs read operations upon a selected memory cell when the selected RWL is enabled by the enable pulse and the selected WWL is enabled by at least one first enable pulse, and the write driver circuit performs a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse.