Memory Multiplexing Techniques for Yield and Area Efficiency
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Solution Overview
Problem
Current memory designs that incorporate redundancy for improved yield face challenges in power, performance, and area efficiency due to the extensive use of processing cores, leading to area inefficiency, negative timing impacts, and excessive power consumption.
Innovation Solution
Implementing memory multiplexing methodologies that enhance architectural layout design of memory circuitry, specifically through single-bank and multi-bank multiplexing schemes, to reduce the impact of redundancy on area, timing, and power consumption, while improving dynamic power, performance, and area efficiency with simpler circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy is incorporated in memory designs for improved yield, then reliability is improved, but area efficiency deteriorates
Solution Approach 1:
The patent merges the redundant memory column with the functional memory column by sharing common circuitry including sense amplifiers, row decoders, and column multiplexers. This consolidation allows the same hardware resources to serve both functional and redundant columns, thereby improving yield through redundancy while minimizing the additional area required.
Solution Approach 2:
The column multiplexer is designed to universally select between functional columns and redundant columns based on operational needs. The same multiplexer circuitry that normally routes data from functional columns can also route data from redundant columns when yield compensation is required, making the system multi-functional without requiring separate dedicated routing paths.
2Reliability
If redundancy is incorporated in memory designs, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent combines the sensing and multiplexing operations for both functional and redundant columns into a single operational sequence. By sharing sense amplifiers and column multiplexers between functional and redundant columns, the patent reduces the total number of power-consuming operations required to access redundant data, thereby mitigating the power overhead of incorporating redundancy.
3Reliability
If redundancy is incorporated in memory designs, then reliability is improved, but timing performance deteriorates
Solution Approach 1:
The patent merges the row decoding and column selection operations for functional and redundant columns into unified circuits. The shared row decoders and column multiplexers eliminate the need for separate decoding paths, ensuring that access to redundant columns does not introduce additional timing delays compared to functional columns.
4Reliability
If separate multiplexer logic is used for redundant columns, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the control logic for selecting between functional and redundant columns into the existing column multiplexer control mechanism. The same control signals that select functional columns also selectively enable redundant columns, eliminating the need for separate control logic and reducing overall device complexity while maintaining yield improvement benefits.
Solution Approach 2:
The column multiplexer is designed with universal selection capability that can identify and route data from either functional columns or redundant columns based on a unified control scheme. This multi-functional design allows the same circuitry to handle both normal operation and yield compensation scenarios without requiring additional dedicated control paths.
Data Source
AI summary
Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.