Variable Resistance Memory Read Circuit Segmentation

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Solution Overview

Problem

Existing non-volatile storage devices face inefficiencies in read operations due to the need for self-reference reading methods that require multiple steps, making quick and accurate data retrieval difficult.

Innovation Solution

A storage device configuration with a memory cell array and a detection circuit that compares resistance values between a first memory cell and a second memory cell within the same memory block, allowing for efficient read operations by using a reference memory cell to determine the data stored in detection target memory cells in two steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If self-reference reading method is used in existing non-volatile storage devices, then data can be read with reasonable accuracy, but the read operation requires multiple steps which reduces efficiency

Engineering Contradiction:
Improvedata reading accuracyVSAvoidread operation efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The memory block is segmented into a reference memory cell region and a main memory cell region. The reference memory cell is physically separated from the main memory cells, allowing independent access and reading operations. This segmentation enables the reference cell to be read separately and used for comparison, improving both accuracy through proper reference comparison and efficiency by allowing parallel or pre-fetched reference readings.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reference memory cell is read in advance before the main memory cells in a memory block. By performing the reference reading operation preliminarily, the reference resistance value is obtained and stored in a register before the actual data reading begins. This preliminary action eliminates the need to wait for reference reading during the data reading process, thereby improving read operation efficiency while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple steps are used for read operations, then accurate data retrieval is possible, but the number of steps increases which slows down the read speed

Engineering Contradiction:
Improvedata retrieval accuracyVSAvoidread speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The reference memory cell is read in advance before the main memory cells. The obtained reference resistance value is stored in a register, preparing the reference data before it is needed for comparison. This preliminary reading action reduces the total read time by eliminating sequential dependencies, thereby increasing read speed while maintaining the accuracy needed for proper data retrieval.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The reading operations are structured to maintain continuous useful action by overlapping or sequencing reads efficiently. The reference cell is read continuously in advance, and its value is held ready in a register, allowing the main memory cells to be read without interruption or waiting time. This continuous operation maintains high read speed while ensuring accurate comparison is possible.

Inventive Principle:
Principle #20Continuity of useful action

3Measurement precision

If reference memory cell is used for each memory block, then reading accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvereading accuracyVSAvoidmemory block structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Each memory block is segmented to include one reference memory cell and multiple main memory cells. This segmentation provides a clear structural organization where the reference cell serves a specific function (providing reference resistance value) while the main cells store data. The segmented structure improves reading accuracy by ensuring each block has its own reference, while the regular repeating pattern keeps device complexity manageable through standardization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reference memory cell structure is designed to be universal across all memory blocks. Each block follows the same pattern with one reference cell and multiple main cells, allowing the same control logic and reading methodology to be applied throughout the device. This universality improves reading accuracy consistently across all blocks while avoiding the need for complex block-specific control circuits, thereby managing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables quick and accurate data reading by reducing the number of steps required for data retrieval and ensuring high accuracy through the use of a reference memory cell for each memory block, thereby improving overall read operation efficiency.

Implementation Method 1

variable resistance memory elements such as a magnetoresistance effect element

Methodology Applied
Scientific EffectMagnetoresistance effect: Magnetoresistance

Data Source

PatentUS11742020B2Storage device
Publication Date: 2023.08.29 KIOXIA CORP
  • US11742020B2 patent drawing
  • US11742020B2 patent drawing
  • US11742020B2 patent drawing

AI summary

A storage device includes a memory cell array in which a plurality of memory cells respectively including a variable resistance memory element are divided into a plurality of memory blocks, the plurality of memory cells including a first memory cell and a second memory cell that are in the same memory block, and a detection circuit. During a read operation in which the first memory cell is a read target, the detection circuit compares a first resistance value, which is a resistance value of the variable resistance memory element in the first memory cell, with a second resistance value, which is a resistance value of the variable resistance memory element in the second memory cell, and determines a value of data stored in the first memory cell based on whether or not the first resistance value is higher or lower than the second resistance value.