Vertical MOSFET Memory Cell Structure With SiGe Source/Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Increasing memory capacity in semiconductor memory devices is difficult due to the limitations of finer processing dimensions, necessitating a new approach to reduce the planar area of memory cells.
Innovation Solution
A vertical structure for access transistors is implemented, combining silicon germanium (SiGe) as source/drain regions with a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) configuration, allowing for a stacked arrangement of access transistors and storage capacitors, reducing the planar area occupied by memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar memory cell structure is used, then manufacturing process is simpler, but memory capacity cannot be increased due to finer processing dimension limitations
Solution Approach 1:
The patent transitions from a conventional planar (2D) memory cell structure to a three-dimensional (3D) vertical structure. The access transistor is configured with its channel extending vertically through the substrate, and the storage capacitor is positioned above the transistor in a stacked arrangement. This dimensional change enables increased memory capacity by utilizing the vertical space, allowing more memory cells to be packed into a smaller planar area without increasing the device footprint.
2Area of stationary object
If vertical structure with SiGe source/drain regions is used, then planar area is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The patent employs silicon germanium (SiGe) material with specific compositional parameters (germanium content of 1-10 atomic percent) to form source/drain regions. This parameter change in material composition enables better lattice matching and reduced defects compared to conventional silicon, facilitating the vertical structure formation. The SiGe regions are formed through selective epitaxial growth processes, allowing precise control of layer thickness and composition to achieve the desired vertical transistor geometry while managing manufacturing complexity.
3Reliability
If vertical MOSFET configuration is implemented, then write and read characteristics are improved, but device complexity increases
Solution Approach 1:
The vertical MOSFET structure is segmented into distinct functional regions: the channel region extending vertically through the substrate, the source/drain regions formed from SiGe material, the gate electrode positioned at the bottom, and the storage capacitor located above. This segmentation allows each component to be optimized independently for its specific function while maintaining overall device performance. The separated regions enable improved electrical characteristics by reducing parasitic effects and enhancing control over the channel, thereby improving write and read characteristics.
Data Source
AI summary
A semiconductor memory device including an access transistor configured as a vertical transistor comprises a channel portion and a pair of source/drain regions; a storage capacitor connected to one of the pair of source/drain regions; a bit line connected to the other of the pair of source/drain regions, a first semiconductor layer provided in the source/drain region to which the bit line is connected. Preferably, the first semiconductor layer comprises SiGe.