Current-Holding Arithmetic Circuit for Low-Power Product-Sum Operation

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Solution Overview

Problem

Artificial neural networks face challenges with increasing power consumption, heat generation, and variations in transistor characteristics as the number of circuits and layers increase, affecting circuit performance and arithmetic operations.

Innovation Solution

A semiconductor device with a hierarchical structure comprising first and second circuits, each with holding portions and driving transistors, that manage current flow based on input potentials to reduce power consumption and minimize temperature sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of circuits and layers in an artificial neural network is increased to improve processing capability, then the arithmetic operation performance is improved, but the power consumption increases

Engineering Contradiction:
Improvearithmetic operation performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple functions into a single circuit element. Specifically, each circuit element performs both storage (holding portion) and computation (arithmetic operation) functions simultaneously, eliminating the need for separate memory and processing units. This merging reduces the total number of circuits required while maintaining arithmetic operation performance, thereby reducing power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The circuit elements are designed to be multi-functional, serving as both memory storage units and arithmetic processing units. The holding portion stores data while the same circuit element performs arithmetic operations on that data, making each element universally applicable for both storage and computation tasks, thus reducing overall power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the number of circuits and layers is increased to improve processing capability, then the arithmetic operation performance is improved, but heat generation increases

Engineering Contradiction:
Improvearithmetic operation performanceVSAvoidheat generation
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

By merging storage and computation functions into a single circuit element, the patent reduces the total number of circuits required. Fewer circuits mean less overall heat generation, while the integrated design allows efficient heat dissipation within each compact element, maintaining arithmetic performance without excessive heat.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If the number of circuits is increased to improve processing capability, then the arithmetic operation performance is improved, but the sensitivity to environmental temperature and transistor variations increases

Engineering Contradiction:
Improvearithmetic operation performanceVSAvoidsensitivity to environmental temperature and transistor variations
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The integration of storage and computation in a single circuit element reduces the number of interconnections and interfaces between components. This minimizes the accumulation of variations from multiple transistors and reduces sensitivity to environmental temperature changes, thereby improving reliability while maintaining arithmetic performance.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12518800B2Semiconductor device performing arithmetic operation
Publication Date: 2026.01.06 SEMICON ENERGY LAB CO LTD
  • US12518800B2 patent drawing
  • US12518800B2 patent drawing
  • US12518800B2 patent drawing

AI summary

A semiconductor device capable of product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding portion and a first transistor, and the second circuit includes a second holding portion and a second transistor. The first and second circuits are each electrically connected to first and second input wirings and first and second wirings. The first holding portion has a function of holding a first current flowing through the first transistor, and the second holding portion has a function of holding a second current flowing through the second transistor. The first and second currents are determined in accordance with first data. When a potential corresponding to second data is input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The amount of current output from the first or second circuit to the first wiring or the second wiring is determined in accordance with the first data and the second data.