Column Select Topology for Multi-Word Memory Blast Writes
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Solution Overview
Problem
The speed of processing units is limited by the latency in reading and writing data to memory, particularly due to row and column changes during operations, which contribute to higher clock cycles.
Innovation Solution
Implementing a 'blast mode' write operation where multiple words are written to a row of memory simultaneously by using additional write drivers and column select circuitry to reduce the number of clock cycles required for writing multiple bitcells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple words are written to memory individually using conventional write operations, then each word is written accurately to its designated location, but the number of clock cycles required increases, reducing throughput
Solution Approach 1:
The patent combines multiple individual write operations into a single consolidated write operation. Multiple words are loaded into a buffer and written to memory simultaneously in one clock cycle, merging what would otherwise be separate sequential operations. This buffering approach allows the system to maintain multiple words ready for writing and execute them together, dramatically improving throughput while reducing the total clock cycles required.
Solution Approach 2:
The patent implements a buffer that loads and holds multiple words in advance before the actual write operation to memory. This preliminary loading of words into the buffer during consecutive clock cycles prepares the data ahead of time, so that when the write operation occurs, multiple words can be transferred to memory in a single clock cycle without waiting for individual word preparation.
2Productivity
If additional write drivers and column select circuitry are added to enable blast mode writing, then write throughput increases, but device complexity increases
Solution Approach 1:
The patent segments the write operation into distinct functional components: a buffer for loading words, multiple write drivers for parallel data output, and column select circuitry for addressing. This segmentation allows each component to be optimized independently and facilitates the parallel writing of multiple words to different columns in memory simultaneously, enabling burst write mode operation.
Solution Approach 2:
The additional write drivers and column select circuitry are designed to work with the existing memory architecture, allowing the same hardware to handle both conventional single-word writes and burst-mode multi-word writes. The column select circuitry can selectively activate different columns based on the write mode, making the extended circuitry multi-functional rather than dedicated to a single operation type.
Data Source
AI summary
A write circuitry may include a first write driver and at least one additional write driver for a set of bitlines coupled to bitcells of a memory; column select circuitry; a first storage element coupled to an input data pin to receive data for storing in the memory; and at least one additional storage element coupled in series with the first storage element. The first storage element and each of the at least one additional storage element are also coupled to a corresponding write driver. The column select circuitry may include a first column select circuitry for the first write driver that selects from a first subset of the set of bitlines; and a second column select circuitry for a second write driver that selects from a second subset of the set of bitlines, where the first subset and the second subset are overlapping sets.