CMOS Under Array Memory Structure for Area Penalty Reduction
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high-density memory devices with efficient area usage and reduced area penalties due to the limitations in the placement and routing of sense amplifiers relative to memory arrays, leading to wasted memory cells and increased chip size.
Innovation Solution
The proposed solution involves a CMOS under array (CuA) memory structure where sense amplifiers are formed under memory arrays, with conductive interconnects routing bit lines to adjacent sense amplifiers, allowing for efficient placement of two sense amplifiers for every two bit lines, reducing area waste and improving array efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sense amplifiers are placed adjacent to memory arrays with direct routing, then routing complexity is reduced, but area penalty increases due to wasted memory cells
Solution Approach 1:
The sense amplifiers are moved from a planar arrangement adjacent to the memory array to a vertical arrangement underneath the memory array. This dimensional change allows the sense amplifiers to be positioned in a different spatial plane, eliminating the need for complex bit line extensions while minimizing the area occupied by support structures.
Solution Approach 2:
Conductive interconnect layers are introduced as intermediary elements to route bit lines from the memory array through the substrate to the sense amplifiers positioned underneath. These interconnect layers act as mediators that enable electrical connection without requiring the sense amplifiers to be physically adjacent to the memory cells.
2Area of stationary object
If sense amplifiers are placed under memory arrays, then area penalty is reduced, but routing complexity increases due to conductive interconnect requirements
Solution Approach 1:
The conductive interconnect layers serve multiple functions: they provide mechanical support for the memory array, enable electrical routing to the sense amplifiers, and facilitate heat dissipation. This multi-functionality reduces the need for separate dedicated routing structures, thereby managing complexity despite the increased routing demands.
Solution Approach 2:
The routing function is segmented across multiple conductive interconnect layers rather than requiring a single complex routing path. Each layer handles specific routing tasks, allowing for modular design and simplifying the overall routing architecture despite the three-dimensional configuration.
3Ease of manufacture
If traditional memory array layout is used, then manufacturing process is simpler, but memory bit density is lower due to area waste
Solution Approach 1:
The sense amplifiers are nested underneath the memory array in a hierarchical arrangement, with the memory array positioned in the upper layer and sense amplifiers in the lower layer. This nesting allows both components to occupy the same horizontal footprint without interfering with each other's operation, thereby maximizing memory bit density while maintaining manufacturing feasibility.
Data Source
AI summary
A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.