Dual-Channel Memory Module Operation via Multiple Data Channels

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Solution Overview

Problem

Current dual in-line memory module (DIMM) technologies face challenges in efficiently accessing memory devices due to signaling limitations and capacity constraints when using multiple DIMMs per data channel, leading to frequency limitations and reduced capacity, especially with newer technologies like DDR5 and HBM2.

Innovation Solution

Implementing a system that allows DIMMs to operate in either dual or single channel modes by using multiple data channels and command buses, with packetized control address commands and reduced pin counts to enhance data access and reduce power consumption, while maintaining full memory bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple DIMMs are used per data channel to increase memory capacity, then memory capacity is improved, but frequency limitations and signaling constraints worsen

Engineering Contradiction:

Improvememory capacityVSAvoidsignaling reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the memory system into multiple independent data channels (first data channel and second data channel), each capable of operating at full frequency. This segmentation allows each channel to maintain signaling reliability while the aggregate system provides increased memory capacity through parallel access paths.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If all DIMM slots are filled to maximize memory capacity, then memory capacity is improved, but power consumption increases

Engineering Contradiction:

Improvememory capacityVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic channel configuration that allows the memory system to adapt between single-channel and dual-channel modes based on operational requirements. This enables the system to use fewer DIMM slots when full capacity is not needed, thereby reducing power consumption while maintaining the ability to scale to full capacity when required.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If single data channel is used to reduce complexity, then device complexity is reduced, but memory bandwidth is limited

Engineering Contradiction:

Improvedata channel complexityVSAvoidmemory bandwidth

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent designs the memory interface with universal components that can operate in multiple configurations. The same memory controller and interface circuitry can function in either single-channel or dual-channel mode, providing multi-functionality that delivers high bandwidth when needed while maintaining simplicity when the full dual-channel capability is not required.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10592445B2Techniques to access or operate a dual in-line memory module via multiple data channels

Publication Date: 2020.03.17 INTEL CORP

AI summary

Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.