Resistive Memory Cells With CMOS Transmission Gates for Higher Write Current
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Solution Overview
Problem
Existing memory devices face challenges in achieving high integrity, non-volatility, and high speed performance, as seen in technologies like DRAM, flash memory, and SRAM, with resistive memory devices like PRAM, NFGM, PoRAM, MRAM, and RRAM not fully addressing these requirements.
Innovation Solution
The resistive memory device incorporates a memory cell array with variable resistor elements and CMOS transmission gates, utilizing two selection transistors of different conductivity types to perform set and reset write operations, enhancing write current magnitude and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional resistive memory devices use single selection transistor configuration, then device complexity is reduced, but write current magnitude is insufficient and performance is limited
Solution Approach 1:
The patent combines two selection transistors with different conductivity types (NMOS and PMOS) to form a CMOS transmission gate configuration. This merging of complementary transistors enables the device to achieve higher write current magnitude by utilizing the complementary conduction characteristics of NMOS and PMOS transistors, while maintaining compact integration. The CMOS transmission gate structure allows for bidirectional current control and enhanced write capability without proportionally increasing device complexity.
Solution Approach 2:
The patent changes the conductivity type parameter of the selection transistors by incorporating both NMOS and PMOS transistors in the CMOS transmission gate. This parameter change enables the device to achieve superior write current magnitude by exploiting the complementary electrical characteristics of the two transistor types, allowing for optimized current flow paths and enhanced write operation performance.
2Productivity
If resistive memory devices operate at high speed, then productivity is improved, but power consumption increases and integrity characteristics deteriorate
Solution Approach 1:
The patent changes the operational parameters of the CMOS transmission gate by utilizing the complementary conductivity types of NMOS and PMOS transistors. This enables the device to achieve high-speed operation with improved power efficiency, as the complementary transistor configuration allows for optimized current control and reduced leakage currents during high-speed write operations, thereby maintaining integrity characteristics while lowering power consumption.
3Manufacturing precision
If resistive memory devices use CMOS transmission gate configuration, then write current magnitude is enhanced and uniformity is improved, but device complexity increases
Solution Approach 1:
The patent changes the transistor configuration parameter by implementing a CMOS transmission gate with complementary NMOS and PMOS transistors. This parameter change enhances the uniformity of resistive memory cells by providing more controlled and consistent current flow through the variable resistor element, improving manufacturing precision and cell-to-cell uniformity while managing device complexity through standard CMOS technology.
Data Source
AI summary
A memory device includes an array of resistive memory cells, row and column decoders, a control circuit and a write/read circuit coupled to the column decoder and the control circuit. The write/read circuit is configured to perform a write operation that transfers write data into a target page of resistive memory cells. A first resistive memory cell includes: a variable resistor element having a first terminal coupled to a first source line, and first and second selection transistors configured in combination as a CMOS transmission gate having a first current carrying terminal coupled to a first bit line, a second current carrying terminal coupled to a second terminal of the variable resistor element, and a gate terminal coupled to a first word line. A first write driver within the write/read circuit is configured to selectively perform a set write operation and a reset write operation on the variable resistor element.