Pseudo-2-port Memory Dual Precharge Circuit Cycle Time Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Pseudo-2-port (P2P) memories face challenges in achieving optimal cycle time due to the need for careful timing of read and write operations to minimize delays and maximize operating frequency.
Innovation Solution
The implementation of dual precharge circuits in a memory circuit system, where one precharge circuit charges bitlines for columns not being written during a write operation, and the second precharge circuit charges bitlines for columns that were written after the write operation is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single precharge circuit is used to charge all bitlines before write operations, then all bitlines are properly charged, but the write wordline pulse width must be long enough to wait for all bitlines to charge, increasing cycle time
Solution Approach 1:
The precharge circuit is segmented into two independent parts: a first precharge circuit that charges bitlines for columns not being written, and a second precharge circuit that charges bitlines for columns being written. This segmentation allows different charging schedules for different bitline groups, enabling the write operation to start when only the necessary bitlines are charged, rather than waiting for all bitlines to charge.
Solution Approach 2:
The first precharge circuit performs preliminary charging of bitlines for columns not being written before the write operation begins. This preliminary action allows these bitlines to be ready in advance without delaying the write pulse, since they don't need to be charged during the critical write timing window.
2Reliability
If bitlines are charged before every write operation, then all bitlines are ready for any operation, but this conservative timing increases the P2P cycle time
Solution Approach 1:
The system dynamically adjusts the charging timing of different bitline groups based on the specific write operation being performed. The first precharge circuit charges bitlines for non-written columns earlier in the cycle, while the second precharge circuit charges bitlines for written columns at the appropriate time. This dynamic timing optimization allows the system to maintain reliability while reducing the overall cycle time and improving operating frequency.
Data Source
AI summary
A memory circuit system and method for using the same are provided. In one example, the memory circuit system includes a memory array, a first precharge circuit, and a second precharge circuit. The memory array writes a first set of columns of the memory array. The first precharge circuit charges bitlines of a second set of columns of the memory array while bitlines of the first set of columns discharge. The first set of columns is different from the second set of columns. The second precharge circuit charges the bitlines of the first set of columns after the memory array has finished writing the first set of columns.