Low Voltage Bit-Cell With Segmented Ports

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Solution Overview

Problem

Six-transistor bit-cells face challenges in low voltage operations due to writability, read-stability, and readability issues, such as internal feedback, distortion on read bit-lines, and slow transistor operation, which hinder effective write and read operations.

Innovation Solution

A twelve-transistor bit-cell design with distinct write-port and read-port circuits, each activated by different threshold voltages, utilizing CMOS transistors to facilitate write and read operations, and power management circuitry that operates in multiple modes to minimize leakage and enhance operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If six-transistor bit-cell design is used, then area is reduced, but low voltage operation capability deteriorates due to writability, read-stability, and readability problems

Engineering Contradiction:
Improvebit-cell areaVSAvoidlow voltage operation reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The bit-cell is segmented into two independent ports: a write-port circuit with four transistors and a read-port circuit with four transistors. Each port can be independently activated by different threshold voltages, allowing the write-port to operate at higher voltages for reliable writing while the read-port operates at lower voltages for low-power reading, thus resolving the low voltage operation reliability issue while maintaining compact area

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different threshold voltages are applied to different parts of the bit-cell: the write-port uses a first threshold voltage optimized for write operations, while the read-port uses a second threshold voltage optimized for read operations. This local differentiation allows each port to operate optimally at its designated voltage level, overcoming the limitations of uniform six-transistor designs at low voltages

Inventive Principle:
Principle #3Local quality

2Use of energy by moving object

If six-transistor bit-cell operates at low voltage, then power consumption is reduced, but read-stability deteriorates due to distortion on read bit-lines

Engineering Contradiction:
Improvepower consumptionVSAvoidread-stability
Core Design Contradiction:
Use of energy by moving objectVSStability of the object's composition

Solution Approach 1:

The read-port circuit is designed with transistors having different threshold voltage characteristics to maintain adequate voltage levels on the read bit-lines during low voltage operation. By carefully selecting and configuring the threshold voltages of the read-port transistors, the circuit maintains read-stability even when operating at reduced power consumption levels

Inventive Principle:
Principle #35Parameter changes

3Use of energy by moving object

If six-transistor bit-cell operates at low voltage, then energy usage is reduced, but readability deteriorates due to slow transistor operation

Engineering Contradiction:
Improveenergy usageVSAvoidtransistor operation speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The read-port circuit uses transistors with optimized threshold voltages that balance low power consumption with adequate switching speed. The threshold voltage of the read-port transistors is specifically tuned to ensure they can switch fast enough to drive the read bit-lines within the required time window, even at low operating voltages, thus maintaining readability while keeping energy usage low

Inventive Principle:
Principle #3Local quality

4Device complexity

If six-transistor bit-cell is used, then device complexity is reduced, but writability deteriorates due to internal feedback on cross-coupled inverters

Engineering Contradiction:
Improvetransistor countVSAvoidwritability
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The write-port circuit is separated from the read-port circuit, with the write-port consisting of four transistors that can be independently controlled. This segmentation allows the write-port to be activated at higher threshold voltages when writing is needed, providing strong write capability that overcomes the internal feedback issue, while the rest of the cell maintains its compact six-transistor-like footprint

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11200946B2Low voltage bit-cell
Publication Date: 2021.12.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11200946B2 patent drawing
  • US11200946B2 patent drawing
  • US11200946B2 patent drawing

AI summary

Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.