Memory Bank Write Wiring Segmentation for Faster Writes

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Solution Overview

Problem

In memory devices, the use of a single pair of write data wirings to drive multiple memory banks leads to significant resistance-capacitance (RC) loading, resulting in signal distortion and reduced writing speed, particularly for banks farther from the global write circuit.

Innovation Solution

The memory device is divided into groups, with each group having separate pairs of write data wirings, reducing RC loading and improving writing speed by optimizing the distribution of capacitance on the wirings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single pair of write data wirings is used to drive multiple memory banks, then device complexity is reduced, but RC loading increases causing signal distortion and reduced writing speed

Engineering Contradiction:

Improvewrite circuit structureVSAvoidwriting speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent divides the memory banks into multiple groups, with each group driven by a separate pair of write data wirings. This segmentation reduces the RC loading on each wiring pair by limiting the number of banks driven per wiring, thereby maintaining signal integrity and writing speed without significantly increasing overall device complexity.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If a single pair of write data wirings is used to drive multiple memory banks, then ease of operation is improved, but signal distortion occurs due to RC loading

Engineering Contradiction:

Improvewrite operation controlVSAvoidsignal transmission accuracy

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent segments memory banks into multiple groups, each with dedicated write data wirings. This reduces RC loading and prevents signal distortion while maintaining operational simplicity through unified control signals. The segmentation ensures reliable signal transmission to all banks without complicating the write operation control mechanism.

Inventive Principle:

Principle #1Segmentation

3Speed

If separate pairs of write data wirings are provided for each memory bank group, then writing speed is improved, but device complexity increases

Engineering Contradiction:

Improvewriting speedVSAvoidwrite wiring structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent implements segmentation by dividing memory banks into groups with dedicated write data wirings. This approach optimizes writing speed by reducing RC loading on each wiring pair while controlling device complexity through systematic grouping. The increased wiring structure is justified by the significant performance improvement in writing speed and signal integrity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12518809B2Memory device with write circuit and method of operating the same

Publication Date: 2026.01.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.