Latching Predecoder for Clocked Memory Word Line Selection
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Solution Overview
Problem
Existing clocked memories face challenges in efficiently selecting word lines due to unreliable timing in initiating the word line selection process, particularly in combining address response and decoded output, often relying on delayed clock signals that prolong detection time unnecessarily.
Innovation Solution
The implementation of latching predecoder circuitry that provides predecoded signals to word line driver logic, allowing immediate resolution of address combinations in response to a clock signal and latching these signals early in the clock cycle, thereby enabling efficient word line selection and preparation for the next selection without needing to maintain the decoded values throughout the entire cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delayed clock signal is used to control word line selection, then the timing reliability is improved, but the detection time is unnecessarily extended
Solution Approach 1:
The predecoder circuitry performs the word line selection decoding action in advance during the first portion of the clock cycle, before the main memory operation begins. This preliminary decoding action eliminates the need to wait for a delayed clock signal, reducing detection time while maintaining timing reliability through the clock-controlled latching mechanism.
2Reliability
If decoded values are maintained throughout the entire clock cycle, then the word line selection is reliable, but the memory operation efficiency is reduced
Solution Approach 1:
The patent extracts the decoded word line selection signal from the main memory operation timeline by providing it during the first portion of the clock cycle. The latched predecoded signal is then removed from active use after the word line is selected, allowing the predecoder to be reset for the next cycle without waiting for the entire clock cycle to complete, thus improving efficiency while maintaining reliability.
3Speed
If the predecoder circuitry is clocked to resolve address combinations immediately, then the word line selection speed is improved, but the latching timing must be precisely controlled
Solution Approach 1:
The latching mechanism is designed to automatically latch the predecoded signal at the appropriate time during the clock cycle without requiring external timing control signals. The clock signal itself serves as both the trigger for decoding and the timing reference for latching, making the system self-regulating and simplifying the timing control complexity while maintaining high selection speed.
Data Source
AI summary
A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.